Csrc/
Csrc/C.CPP
Csrc/C.DSP
Csrc/C.DSW
Csrc/C.ncb
Csrc/C.OPT
Csrc/C.PLG
Csrc/Debug/
Csrc/Debug/C.exe
Csrc/Debug/C.ilk
Csrc/Debug/C.obj
Csrc/Debug/C.pch
Csrc/Debug/C.pdb
Csrc/Debug/vc60.idb
Csrc/Debug/vc60.pdb
Msrc/
Msrc/code.s
project/
project/Add_tb.jpg
project/ALUControl_tb.jpg
project/ALU_tb.jpg
project/Control_tb.jpg
project/Counter_tb.jpg
project/DataMemory_tb.jpg
project/InsMemory_tb.jpg
project/Mux_tb.jpg
project/PC_tb.jpg
project/project.pdf
project/project.wps
project/Registers_tb.jpg
project/ShiftLeft2_tb.jpg
project/SignExtend_tb.jpg
reference/
reference/0_2 常用模块的Verilog HDL设计.pdf
reference/chart.jpg
reference/chart.psd
reference/MIPS ISA.pdf
reference/MIPS Reference Card.pdf
reference/SPIM.pdf
reference/True Value.xls
reference/Verilog HDL硬件描述语言（入门级）.pdf
reference/verilog_内存建模.pdf
reference/Verilog代码书写规范.pdf
reference/数字系统设计2_2012Project1.doc
reference/数字系统设计2_2012Project1.pdf
sim/
sim/Add_test.cr.mti
sim/Add_test.mpf
sim/ALUCountrol_test.cr.mti
sim/ALUCountrol_test.mpf
sim/ALU_test.cr.mti
sim/ALU_test.mpf
sim/Control_test.cr.mti
sim/Control_test.mpf
sim/Counter_test.cr.mti
sim/Counter_test.mpf
sim/CPU.cr.mti
sim/CPU.mpf
sim/DataMemory.txt
sim/DataMemory_test.cr.mti
sim/DataMemory_test.mpf
sim/InsMemory.txt
sim/InsMemory_test.cr.mti
sim/InsMemory_test.mpf
sim/Mux_test.cr.mti
sim/Mux_test.mpf
sim/PC_test.cr.mti
sim/PC_test.mpf
sim/Registers.txt
sim/Registers_test.cr.mti
sim/Registers_test.mpf
sim/ShiftLeft2_test.cr.mti
sim/ShiftLeft2_test.mpf
sim/SignExtend_test.cr.mti
sim/SignExtend_test.mpf
sim/transcript
sim/vsim.wlf
sim/vsim_stacktrace.vstf
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sim