文件名称:pipelined-CPU
-
所属分类:
- 标签属性:
- 上传时间:2013-06-10
-
文件大小:7.27mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab28-他人/
lab28-他人/ISE/
lab28-他人/ISE/DataRAM.asy
lab28-他人/ISE/DataRAM.ngc
lab28-他人/ISE/DataRAM.sym
lab28-他人/ISE/DataRAM.v
lab28-他人/ISE/DataRAM.veo
lab28-他人/ISE/DataRAM.vhd
lab28-他人/ISE/DataRAM.vho
lab28-他人/ISE/DataRAM.xco
lab28-他人/ISE/DataRAM_flist.txt
lab28-他人/ISE/DataRAM_readme.txt
lab28-他人/ISE/DataRAM_xmdf.tcl
lab28-他人/ISE/mipspipelinecpu.bgn
lab28-他人/ISE/mipspipelinecpu.bit
lab28-他人/ISE/MipsPipelineCPU.bld
lab28-他人/ISE/MipsPipelineCPU.cel
lab28-他人/ISE/MipsPipelineCPU.cmd_log
lab28-他人/ISE/mipspipelinecpu.drc
lab28-他人/ISE/MipsPipelineCPU.ise
lab28-他人/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/ISE/MipsPipelineCPU.lso
lab28-他人/ISE/MipsPipelineCPU.ncd
lab28-他人/ISE/MipsPipelineCPU.ngc
lab28-他人/ISE/MipsPipelineCPU.ngd
lab28-他人/ISE/MipsPipelineCPU.ngr
lab28-他人/ISE/MipsPipelineCPU.ntrc_log
lab28-他人/ISE/MipsPipelineCPU.pad
lab28-他人/ISE/MipsPipelineCPU.par
lab28-他人/ISE/MipsPipelineCPU.pcf
lab28-他人/ISE/MipsPipelineCPU.prj
lab28-他人/ISE/MipsPipelineCPU.restore
lab28-他人/ISE/MipsPipelineCPU.stx
lab28-他人/ISE/MipsPipelineCPU.syr
lab28-他人/ISE/mipspipelinecpu.twr
lab28-他人/ISE/mipspipelinecpu.twx
lab28-他人/ISE/MipsPipelineCPU.ucf
lab28-他人/ISE/MipsPipelineCPU.unroutes
lab28-他人/ISE/MipsPipelineCPU.ut
lab28-他人/ISE/MipsPipelineCPU.xpi
lab28-他人/ISE/MipsPipelineCPU.xst
lab28-他人/ISE/MipsPipelineCPU_guide.ncd
lab28-他人/ISE/MipsPipelineCPU_map.map
lab28-他人/ISE/MipsPipelineCPU_map.mrp
lab28-他人/ISE/MipsPipelineCPU_map.ncd
lab28-他人/ISE/MipsPipelineCPU_map.ngm
lab28-他人/ISE/MipsPipelineCPU_pad.csv
lab28-他人/ISE/MipsPipelineCPU_pad.txt
lab28-他人/ISE/MipsPipelineCPU_prev_built.ngd
lab28-他人/ISE/MipsPipelineCPU_summary.html
lab28-他人/ISE/MipsPipelineCPU_summary.xml
lab28-他人/ISE/MipsPipelineCPU_usage.xml
lab28-他人/ISE/templates/
lab28-他人/ISE/templates/coregen.xml
lab28-他人/ISE/tmp/
lab28-他人/ISE/tmp/_cg/
lab28-他人/ISE/transcript
lab28-他人/ISE/xst/
lab28-他人/ISE/xst/dump.xst/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/notopt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/opt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ntrc.scr
lab28-他人/ISE/xst/projnav.tmp/
lab28-他人/ISE/xst/work/
lab28-他人/ISE/xst/work/hdllib.ref
lab28-他人/ISE/xst/work/vlg0E/
lab28-他人/ISE/xst/work/vlg0E/adder__32bits.bin
lab28-他人/ISE/xst/work/vlg1E/
lab28-他人/ISE/xst/work/vlg1E/_data_r_a_m.bin
lab28-他人/ISE/xst/work/vlg1F/
lab28-他人/ISE/xst/work/vlg1F/_d___f_f.bin
lab28-他人/ISE/xst/work/vlg27/
lab28-他人/ISE/xst/work/vlg27/mux__2to1.bin
lab28-他人/ISE/xst/work/vlg2A/
lab28-他人/ISE/xst/work/vlg2A/_a_l_u.bin
lab28-他人/ISE/xst/work/vlg2F/
lab28-他人/ISE/xst/work/vlg2F/_mips_pipeline_c_p_u.bin
lab28-他人/ISE/xst/work/vlg30/
lab28-他人/ISE/xst/work/vlg30/_decode.bin
lab28-他人/ISE/xst/work/vlg31/
lab28-他人/ISE/xst/work/vlg31/_e_x.bin
lab28-他人/ISE/xst/work/vlg31/_i_d.bin
lab28-他人/ISE/xst/work/vlg33/
lab28-他人/ISE/xst/work/vlg33/_i_f.bin
lab28-他人/ISE/xst/work/vlg54/
lab28-他人/ISE/xst/work/vlg54/adder.bin
lab28-他人/ISE/xst/work/vlg66/
lab28-他人/ISE/xst/work/vlg66/_d___f_f_r_e.bin
lab28-他人/ISE/xst/work/vlg6D/
lab28-他人/ISE/xst/work/vlg6D/_d___f_f_r.bin
lab28-他人/ISE/xst/work/vlg73/
lab28-他人/ISE/xst/work/vlg73/_multi_registers.bin
lab28-他人/ISE/xst/work/vlg7C/
lab28-他人/ISE/xst/work/vlg7C/_instruction_r_o_m.bin
lab28-他人/ISE/_impact.cmd
lab28-他人/ISE/_impact.log
lab28-他人/ISE/_ngo/
lab28-他人/ISE/_ngo/netlist.lst
lab28-他人/ISE/_xmsgs/
lab28-他人/ISE/_xmsgs/bitgen.xmsgs
lab28-他人/ISE/_xmsgs/map.xmsgs
lab28-他人/ISE/_xmsgs/ngdbuild.xmsgs
lab28-他人/ISE/_xmsgs/par.xmsgs
lab28-他人/ISE/_xmsgs/trce.xmsgs
lab28-他人/ISE/_xmsgs/xst.xmsgs
lab28-他人/PipelineCPU/
lab28-他人/PipelineCPU/ISE/
lab28-他人/PipelineCPU/ISE/DataRAM.asy
lab28-他人/PipelineCPU/ISE/DataRAM.ngc
lab28-他人/PipelineCPU/ISE/DataRAM.sym
lab28-他人/PipelineCPU/ISE/DataRAM.v
lab28-他人/PipelineCPU/ISE/DataRAM.veo
lab28-他人/PipelineCPU/ISE/DataRAM.vhd
lab28-他人/PipelineCPU/ISE/DataRAM.vho
lab28-他人/PipelineCPU/ISE/DataRAM.xco
lab28-他人/PipelineCPU/ISE/DataRAM_flist.txt
lab28-他人/PipelineCPU/ISE/DataRAM_readme.txt
lab28-他人/PipelineCPU/ISE/DataRAM_xmdf.tcl
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.restore
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU_summary.html
lab28-他人/PipelineCPU/ISE/templates/
lab28-他人/PipelineCPU/ISE/templates/coregen.xml
lab28-他人/PipelineCPU/ISE/tmp/
lab28-他人/PipelineCPU/ISE/tmp/_cg/
lab28-他人/PipelineCPU/ISE/_xmsgs/
lab28-他人/PipelineCPU/SIM/
lab28-他人/PipelineCPU/SIM/ALU/
lab28-他人/PipelineCPU/SIM/ALU/adder.v
lab28-他人/PipelineCPU/SIM/ALU/adder_32bits.v
lab28-他人/PipelineCPU/SIM/ALU/ALU.cr.mti
lab28-他人/PipelineCPU/SIM/ALU/ALU.mpf
lab28-他人/PipelineCPU/SIM/ALU/ALU.v
lab28-他人/PipelineCPU/SIM/ALU/ALU.v.bak
lab28-他人/PipelineCPU/SIM/ALU/ALU_tb.v
lab28-他人/PipelineCPU/SIM/ALU/mux_2to1.v
lab28-他人/PipelineCPU/SIM/ALU/transcript
lab28-他人/PipelineCPU/SIM/ALU/vsim.wlf
lab28-他人/PipelineCPU/SIM/ALU/work/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.asm
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.rw
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/_primary.dat
lab28-他人/Pipel
lab28-他人/ISE/
lab28-他人/ISE/DataRAM.asy
lab28-他人/ISE/DataRAM.ngc
lab28-他人/ISE/DataRAM.sym
lab28-他人/ISE/DataRAM.v
lab28-他人/ISE/DataRAM.veo
lab28-他人/ISE/DataRAM.vhd
lab28-他人/ISE/DataRAM.vho
lab28-他人/ISE/DataRAM.xco
lab28-他人/ISE/DataRAM_flist.txt
lab28-他人/ISE/DataRAM_readme.txt
lab28-他人/ISE/DataRAM_xmdf.tcl
lab28-他人/ISE/mipspipelinecpu.bgn
lab28-他人/ISE/mipspipelinecpu.bit
lab28-他人/ISE/MipsPipelineCPU.bld
lab28-他人/ISE/MipsPipelineCPU.cel
lab28-他人/ISE/MipsPipelineCPU.cmd_log
lab28-他人/ISE/mipspipelinecpu.drc
lab28-他人/ISE/MipsPipelineCPU.ise
lab28-他人/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/ISE/MipsPipelineCPU.lso
lab28-他人/ISE/MipsPipelineCPU.ncd
lab28-他人/ISE/MipsPipelineCPU.ngc
lab28-他人/ISE/MipsPipelineCPU.ngd
lab28-他人/ISE/MipsPipelineCPU.ngr
lab28-他人/ISE/MipsPipelineCPU.ntrc_log
lab28-他人/ISE/MipsPipelineCPU.pad
lab28-他人/ISE/MipsPipelineCPU.par
lab28-他人/ISE/MipsPipelineCPU.pcf
lab28-他人/ISE/MipsPipelineCPU.prj
lab28-他人/ISE/MipsPipelineCPU.restore
lab28-他人/ISE/MipsPipelineCPU.stx
lab28-他人/ISE/MipsPipelineCPU.syr
lab28-他人/ISE/mipspipelinecpu.twr
lab28-他人/ISE/mipspipelinecpu.twx
lab28-他人/ISE/MipsPipelineCPU.ucf
lab28-他人/ISE/MipsPipelineCPU.unroutes
lab28-他人/ISE/MipsPipelineCPU.ut
lab28-他人/ISE/MipsPipelineCPU.xpi
lab28-他人/ISE/MipsPipelineCPU.xst
lab28-他人/ISE/MipsPipelineCPU_guide.ncd
lab28-他人/ISE/MipsPipelineCPU_map.map
lab28-他人/ISE/MipsPipelineCPU_map.mrp
lab28-他人/ISE/MipsPipelineCPU_map.ncd
lab28-他人/ISE/MipsPipelineCPU_map.ngm
lab28-他人/ISE/MipsPipelineCPU_pad.csv
lab28-他人/ISE/MipsPipelineCPU_pad.txt
lab28-他人/ISE/MipsPipelineCPU_prev_built.ngd
lab28-他人/ISE/MipsPipelineCPU_summary.html
lab28-他人/ISE/MipsPipelineCPU_summary.xml
lab28-他人/ISE/MipsPipelineCPU_usage.xml
lab28-他人/ISE/templates/
lab28-他人/ISE/templates/coregen.xml
lab28-他人/ISE/tmp/
lab28-他人/ISE/tmp/_cg/
lab28-他人/ISE/transcript
lab28-他人/ISE/xst/
lab28-他人/ISE/xst/dump.xst/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/notopt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ngx/opt/
lab28-他人/ISE/xst/dump.xst/MipsPipelineCPU.prj/ntrc.scr
lab28-他人/ISE/xst/projnav.tmp/
lab28-他人/ISE/xst/work/
lab28-他人/ISE/xst/work/hdllib.ref
lab28-他人/ISE/xst/work/vlg0E/
lab28-他人/ISE/xst/work/vlg0E/adder__32bits.bin
lab28-他人/ISE/xst/work/vlg1E/
lab28-他人/ISE/xst/work/vlg1E/_data_r_a_m.bin
lab28-他人/ISE/xst/work/vlg1F/
lab28-他人/ISE/xst/work/vlg1F/_d___f_f.bin
lab28-他人/ISE/xst/work/vlg27/
lab28-他人/ISE/xst/work/vlg27/mux__2to1.bin
lab28-他人/ISE/xst/work/vlg2A/
lab28-他人/ISE/xst/work/vlg2A/_a_l_u.bin
lab28-他人/ISE/xst/work/vlg2F/
lab28-他人/ISE/xst/work/vlg2F/_mips_pipeline_c_p_u.bin
lab28-他人/ISE/xst/work/vlg30/
lab28-他人/ISE/xst/work/vlg30/_decode.bin
lab28-他人/ISE/xst/work/vlg31/
lab28-他人/ISE/xst/work/vlg31/_e_x.bin
lab28-他人/ISE/xst/work/vlg31/_i_d.bin
lab28-他人/ISE/xst/work/vlg33/
lab28-他人/ISE/xst/work/vlg33/_i_f.bin
lab28-他人/ISE/xst/work/vlg54/
lab28-他人/ISE/xst/work/vlg54/adder.bin
lab28-他人/ISE/xst/work/vlg66/
lab28-他人/ISE/xst/work/vlg66/_d___f_f_r_e.bin
lab28-他人/ISE/xst/work/vlg6D/
lab28-他人/ISE/xst/work/vlg6D/_d___f_f_r.bin
lab28-他人/ISE/xst/work/vlg73/
lab28-他人/ISE/xst/work/vlg73/_multi_registers.bin
lab28-他人/ISE/xst/work/vlg7C/
lab28-他人/ISE/xst/work/vlg7C/_instruction_r_o_m.bin
lab28-他人/ISE/_impact.cmd
lab28-他人/ISE/_impact.log
lab28-他人/ISE/_ngo/
lab28-他人/ISE/_ngo/netlist.lst
lab28-他人/ISE/_xmsgs/
lab28-他人/ISE/_xmsgs/bitgen.xmsgs
lab28-他人/ISE/_xmsgs/map.xmsgs
lab28-他人/ISE/_xmsgs/ngdbuild.xmsgs
lab28-他人/ISE/_xmsgs/par.xmsgs
lab28-他人/ISE/_xmsgs/trce.xmsgs
lab28-他人/ISE/_xmsgs/xst.xmsgs
lab28-他人/PipelineCPU/
lab28-他人/PipelineCPU/ISE/
lab28-他人/PipelineCPU/ISE/DataRAM.asy
lab28-他人/PipelineCPU/ISE/DataRAM.ngc
lab28-他人/PipelineCPU/ISE/DataRAM.sym
lab28-他人/PipelineCPU/ISE/DataRAM.v
lab28-他人/PipelineCPU/ISE/DataRAM.veo
lab28-他人/PipelineCPU/ISE/DataRAM.vhd
lab28-他人/PipelineCPU/ISE/DataRAM.vho
lab28-他人/PipelineCPU/ISE/DataRAM.xco
lab28-他人/PipelineCPU/ISE/DataRAM_flist.txt
lab28-他人/PipelineCPU/ISE/DataRAM_readme.txt
lab28-他人/PipelineCPU/ISE/DataRAM_xmdf.tcl
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU.restore
lab28-他人/PipelineCPU/ISE/MipsPipelineCPU_summary.html
lab28-他人/PipelineCPU/ISE/templates/
lab28-他人/PipelineCPU/ISE/templates/coregen.xml
lab28-他人/PipelineCPU/ISE/tmp/
lab28-他人/PipelineCPU/ISE/tmp/_cg/
lab28-他人/PipelineCPU/ISE/_xmsgs/
lab28-他人/PipelineCPU/SIM/
lab28-他人/PipelineCPU/SIM/ALU/
lab28-他人/PipelineCPU/SIM/ALU/adder.v
lab28-他人/PipelineCPU/SIM/ALU/adder_32bits.v
lab28-他人/PipelineCPU/SIM/ALU/ALU.cr.mti
lab28-他人/PipelineCPU/SIM/ALU/ALU.mpf
lab28-他人/PipelineCPU/SIM/ALU/ALU.v
lab28-他人/PipelineCPU/SIM/ALU/ALU.v.bak
lab28-他人/PipelineCPU/SIM/ALU/ALU_tb.v
lab28-他人/PipelineCPU/SIM/ALU/mux_2to1.v
lab28-他人/PipelineCPU/SIM/ALU/transcript
lab28-他人/PipelineCPU/SIM/ALU/vsim.wlf
lab28-他人/PipelineCPU/SIM/ALU/work/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.asm
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/verilog.rw
lab28-他人/PipelineCPU/SIM/ALU/work/@a@l@u/_primary.dat
lab28-他人/Pipel
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.