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文件名称:emif_tt

  • 所属分类：
    Communication
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2013-08-31
  • 文件大小：
    650kb
  • 已下载：
    1次
  • 提 供 者：
    董****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d
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下载文件列表

emif_tt/
emif_tt/Thumbs.db
emif_tt/sim/
emif_tt/sim/dec_data.txt
emif_tt/sim/emif_tt.cr.mti
emif_tt/sim/emif_tt.mpf
emif_tt/sim/rom_data_fft.mif
emif_tt/sim/rom_data_fft_ini.mif
emif_tt/sim/rom_data_fft_ini.ver
emif_tt/sim/rom_data_ini.mif
emif_tt/sim/vsim.wlf
emif_tt/sim/work/
emif_tt/sim/work/_info
emif_tt/sim/work/_temp/
emif_tt/sim/work/_vmake
emif_tt/sim/work/butterfly/
emif_tt/sim/work/butterfly/_primary.dat
emif_tt/sim/work/butterfly/_primary.dbs
emif_tt/sim/work/butterfly/_primary.vhd
emif_tt/sim/work/butterfly/verilog.asm
emif_tt/sim/work/butterfly/verilog.rw
emif_tt/sim/work/control/
emif_tt/sim/work/control/_primary.dat
emif_tt/sim/work/control/_primary.dbs
emif_tt/sim/work/control/_primary.vhd
emif_tt/sim/work/control/verilog.asm
emif_tt/sim/work/control/verilog.rw
emif_tt/sim/work/data_input/
emif_tt/sim/work/data_input/_primary.dat
emif_tt/sim/work/data_input/_primary.dbs
emif_tt/sim/work/data_input/_primary.vhd
emif_tt/sim/work/data_input/verilog.asm
emif_tt/sim/work/data_input/verilog.rw
emif_tt/sim/work/data_output/
emif_tt/sim/work/data_output/_primary.dat
emif_tt/sim/work/data_output/_primary.dbs
emif_tt/sim/work/data_output/_primary.vhd
emif_tt/sim/work/data_output/verilog.asm
emif_tt/sim/work/data_output/verilog.rw
emif_tt/sim/work/emif_brg/
emif_tt/sim/work/emif_brg/_primary.dat
emif_tt/sim/work/emif_brg/_primary.dbs
emif_tt/sim/work/emif_brg/_primary.vhd
emif_tt/sim/work/emif_brg/verilog.asm
emif_tt/sim/work/emif_brg/verilog.rw
emif_tt/sim/work/fft/
emif_tt/sim/work/fft/_primary.dat
emif_tt/sim/work/fft/_primary.dbs
emif_tt/sim/work/fft/_primary.vhd
emif_tt/sim/work/fft/verilog.asm
emif_tt/sim/work/fft/verilog.rw
emif_tt/sim/work/fifo_out/
emif_tt/sim/work/fifo_out/_primary.dat
emif_tt/sim/work/fifo_out/_primary.dbs
emif_tt/sim/work/fifo_out/_primary.vhd
emif_tt/sim/work/fifo_out/verilog.asm
emif_tt/sim/work/fifo_out/verilog.rw
emif_tt/sim/work/mult16x16/
emif_tt/sim/work/mult16x16/_primary.dat
emif_tt/sim/work/mult16x16/_primary.dbs
emif_tt/sim/work/mult16x16/_primary.vhd
emif_tt/sim/work/mult16x16/verilog.asm
emif_tt/sim/work/mult16x16/verilog.rw
emif_tt/sim/work/overflow_detect/
emif_tt/sim/work/overflow_detect/_primary.dat
emif_tt/sim/work/overflow_detect/_primary.dbs
emif_tt/sim/work/overflow_detect/_primary.vhd
emif_tt/sim/work/overflow_detect/verilog.asm
emif_tt/sim/work/overflow_detect/verilog.rw
emif_tt/sim/work/ram64x36_dp/
emif_tt/sim/work/ram64x36_dp/_primary.dat
emif_tt/sim/work/ram64x36_dp/_primary.dbs
emif_tt/sim/work/ram64x36_dp/_primary.vhd
emif_tt/sim/work/ram64x36_dp/verilog.asm
emif_tt/sim/work/ram64x36_dp/verilog.rw
emif_tt/sim/work/reg_ctrl_fft/
emif_tt/sim/work/reg_ctrl_fft/_primary.dat
emif_tt/sim/work/reg_ctrl_fft/_primary.dbs
emif_tt/sim/work/reg_ctrl_fft/_primary.vhd
emif_tt/sim/work/reg_ctrl_fft/verilog.asm
emif_tt/sim/work/reg_ctrl_fft/verilog.rw
emif_tt/sim/work/rom64@x32/
emif_tt/sim/work/rom64@x32/_primary.dat
emif_tt/sim/work/rom64@x32/_primary.dbs
emif_tt/sim/work/rom64@x32/_primary.vhd
emif_tt/sim/work/rom64@x32/verilog.asm
emif_tt/sim/work/rom64@x32/verilog.rw
emif_tt/sim/work/rom_data_fft/
emif_tt/sim/work/rom_data_fft/_primary.dat
emif_tt/sim/work/rom_data_fft/_primary.dbs
emif_tt/sim/work/rom_data_fft/_primary.vhd
emif_tt/sim/work/rom_data_fft/verilog.asm
emif_tt/sim/work/rom_data_fft/verilog.rw
emif_tt/sim/work/shift/
emif_tt/sim/work/shift/_primary.dat
emif_tt/sim/work/shift/_primary.dbs
emif_tt/sim/work/shift/_primary.vhd
emif_tt/sim/work/shift/verilog.asm
emif_tt/sim/work/shift/verilog.rw
emif_tt/sim/work/tb_fft/
emif_tt/sim/work/tb_fft/_primary.dat
emif_tt/sim/work/tb_fft/_primary.dbs
emif_tt/sim/work/tb_fft/_primary.vhd
emif_tt/sim/work/tb_fft/verilog.asm
emif_tt/sim/work/tb_fft/verilog.rw
emif_tt/src/
emif_tt/src/64x32.mif
emif_tt/src/butterfly.v
emif_tt/src/control.v
emif_tt/src/data_input.v
emif_tt/src/data_output.v
emif_tt/src/emif_brg.v
emif_tt/src/fft.v
emif_tt/src/fifo_out.v
emif_tt/src/mult16x16.v
emif_tt/src/overflow_detect.v
emif_tt/src/ram64x36_dp.v
emif_tt/src/reg_ctrl_fft.v
emif_tt/src/rom64X32.v
emif_tt/src/rom_data_fft.v
emif_tt/src/shift.v
emif_tt/src/tb_fft.v
emif_tt/异步写.bmp
emif_tt/异步读.bmp

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