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文件名称:Chapter-12

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12.2 ATA主机控制器设计

12.3 ATA主机控制器Testbench设计 -12.2 ATA host controller design 12.3 ATA host controller Testbench Design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter-12/ata/ata.cr.mti
Chapter-12/ata/ata.mpf
Chapter-12/ata/atahost_controller.v
Chapter-12/ata/atahost_pio_tctrl.v
Chapter-12/ata/atahost_top.v
Chapter-12/ata/atahost_wb_slave.v
Chapter-12/ata/ata_device.v
Chapter-12/ata/chart/Thumbs.db
Chapter-12/ata/chart/图12-10.bmp
Chapter-12/ata/chart/图12-14.bmp
Chapter-12/ata/chart/图12-15.bmp
Chapter-12/ata/chart/图12-16.bmp
Chapter-12/ata/chart/图12-3.bmp
Chapter-12/ata/chart/图12-4.bmp
Chapter-12/ata/chart/图12-5.bmp
Chapter-12/ata/chart/图12-7.bmp
Chapter-12/ata/chart/图12-8.bmp
Chapter-12/ata/ro_cnt.v
Chapter-12/ata/test_bench_top.v
Chapter-12/ata/timescale.v
Chapter-12/ata/transcript
Chapter-12/ata/ud_cnt.v
Chapter-12/ata/vsim.wlf
Chapter-12/ata/wave/atahost_controller.bmp
Chapter-12/ata/wave/atahost_pio_tctrl.bmp
Chapter-12/ata/wave/atahost_top.bmp
Chapter-12/ata/wave/atahost_wb_slave.bmp
Chapter-12/ata/wave/ata_device.bmp
Chapter-12/ata/wave/ro_cnt.bmp
Chapter-12/ata/wave/test_bench_top.bmp
Chapter-12/ata/wave/Thumbs.db
Chapter-12/ata/wb_mast_model.v
Chapter-12/ata/wb_model_defines.v
Chapter-12/ata/wb_slv_model.v
Chapter-12/ata/work/atahost_controller/verilog.asm
Chapter-12/ata/work/atahost_controller/_primary.dat
Chapter-12/ata/work/atahost_controller/_primary.vhd
Chapter-12/ata/work/atahost_pio_tctrl/verilog.asm
Chapter-12/ata/work/atahost_pio_tctrl/_primary.dat
Chapter-12/ata/work/atahost_pio_tctrl/_primary.vhd
Chapter-12/ata/work/atahost_top/verilog.asm
Chapter-12/ata/work/atahost_top/_primary.dat
Chapter-12/ata/work/atahost_top/_primary.vhd
Chapter-12/ata/work/atahost_wb_slave/verilog.asm
Chapter-12/ata/work/atahost_wb_slave/_primary.dat
Chapter-12/ata/work/atahost_wb_slave/_primary.vhd
Chapter-12/ata/work/ata_device/verilog.asm
Chapter-12/ata/work/ata_device/_primary.dat
Chapter-12/ata/work/ata_device/_primary.vhd
Chapter-12/ata/work/ro_cnt/verilog.asm
Chapter-12/ata/work/ro_cnt/_primary.dat
Chapter-12/ata/work/ro_cnt/_primary.vhd
Chapter-12/ata/work/ro_cnt1/verilog.asm
Chapter-12/ata/work/ro_cnt1/_primary.dat
Chapter-12/ata/work/ro_cnt1/_primary.vhd
Chapter-12/ata/work/test_bench_top/verilog.asm
Chapter-12/ata/work/test_bench_top/_primary.dat
Chapter-12/ata/work/test_bench_top/_primary.vhd
Chapter-12/ata/work/ud_cnt/verilog.asm
Chapter-12/ata/work/ud_cnt/_primary.dat
Chapter-12/ata/work/ud_cnt/_primary.vhd
Chapter-12/ata/work/wb_mast/verilog.asm
Chapter-12/ata/work/wb_mast/_primary.dat
Chapter-12/ata/work/wb_mast/_primary.vhd
Chapter-12/ata/work/wb_slv/verilog.asm
Chapter-12/ata/work/wb_slv/_primary.dat
Chapter-12/ata/work/wb_slv/_primary.vhd
Chapter-12/ata/work/_info
Chapter-12/ata/work/atahost_controller
Chapter-12/ata/work/atahost_pio_tctrl
Chapter-12/ata/work/atahost_top
Chapter-12/ata/work/atahost_wb_slave
Chapter-12/ata/work/ata_device
Chapter-12/ata/work/ro_cnt
Chapter-12/ata/work/ro_cnt1
Chapter-12/ata/work/test_bench_top
Chapter-12/ata/work/ud_cnt
Chapter-12/ata/work/wb_mast
Chapter-12/ata/work/wb_slv
Chapter-12/ata/chart
Chapter-12/ata/wave
Chapter-12/ata/work
Chapter-12/ata
Chapter-12

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