Process variations have increased significantly with scaling technologies. This

has led to deviations in analog circuit performance from their expected values.

For submicron design, it is essential to simulate the circuit at all process

corners for yield verification. In this work we develop a methodology based

upon a sensitivity analysis of transistor mismatch to circuit performance for

statistical design parameter estimation. This methodology has been implemented

in a CAD tool. With the objective of rapid simulation, the performance of a

circuit under process variation can be effectively estimated using the tool while

achieving a significant speedup over conventional Monte Carlo methods.