文件名称:traffic-light
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- 上传时间：2015-03-24
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文件大小：3.32mb
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设计任务：设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替运行。
设计要求：
1.要求黄灯先亮5秒，才能变换运行车道并且黄灯亮时另一干道的红灯按1Hz的频率闪烁。
2.要求通行时间及黄灯亮的时间均可在60秒内任意设定。
3.要求交通灯控制电路可以手动控制立即进入特殊运行状态，即两条道上红灯全亮，时钟停止计时。当特殊运行状态结束后，系统复原，继续正常运行。
-Design tasks: Design a crossroads of traffic light control circuit, requiring vehicle lanes and B. A two-lane road cross alternately run. Design requirements: 1. Require bright yellow first five seconds to change lanes and running a red light yellow light by the frequency of 1Hz other roads flashes. 2. Demands that the passage of time and the yellow light time can be set within 60 seconds. 3. Requests the traffic light control circuit can manually control immediately enter the special operation, that two trail-red light, the clock will stop the clock. After the end of the special operation status, system recovery, continue to operate normally.
设计要求：
1.要求黄灯先亮5秒，才能变换运行车道并且黄灯亮时另一干道的红灯按1Hz的频率闪烁。
2.要求通行时间及黄灯亮的时间均可在60秒内任意设定。
3.要求交通灯控制电路可以手动控制立即进入特殊运行状态，即两条道上红灯全亮，时钟停止计时。当特殊运行状态结束后，系统复原，继续正常运行。
-Design tasks: Design a crossroads of traffic light control circuit, requiring vehicle lanes and B. A two-lane road cross alternately run. Design requirements: 1. Require bright yellow first five seconds to change lanes and running a red light yellow light by the frequency of 1Hz other roads flashes. 2. Demands that the passage of time and the yellow light time can be set within 60 seconds. 3. Requests the traffic light control circuit can manually control immediately enter the special operation, that two trail-red light, the clock will stop the clock. After the end of the special operation status, system recovery, continue to operate normally.
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课设/
课设/v3/
课设/v3/Verilog1.asm.rpt
课设/v3/Verilog1.done
课设/v3/Verilog1.dpf
课设/v3/Verilog1.eda.rpt
课设/v3/Verilog1.fit.rpt
课设/v3/Verilog1.fit.summary
课设/v3/Verilog1.flow.rpt
课设/v3/Verilog1.map.rpt
课设/v3/Verilog1.map.smsg
课设/v3/Verilog1.map.summary
课设/v3/Verilog1.pin
课设/v3/Verilog1.qpf
课设/v3/Verilog1.qsf
课设/v3/Verilog1.qsf.bak
课设/v3/Verilog1.qws
课设/v3/Verilog1.sim.rpt
课设/v3/Verilog1.sof
课设/v3/Verilog1.sta.rpt
课设/v3/Verilog1.sta.summary
课设/v3/Verilog1.v
课设/v3/Verilog1.v.bak
课设/v3/Verilog1.vwf
课设/v3/Waveform1.vwf
课设/v3/db/
课设/v3/db/Verilog1.(0).cnf.cdb
课设/v3/db/Verilog1.(0).cnf.hdb
课设/v3/db/Verilog1.(1).cnf.cdb
课设/v3/db/Verilog1.(1).cnf.hdb
课设/v3/db/Verilog1.(2).cnf.cdb
课设/v3/db/Verilog1.(2).cnf.hdb
课设/v3/db/Verilog1.(3).cnf.cdb
课设/v3/db/Verilog1.(3).cnf.hdb
课设/v3/db/Verilog1.(4).cnf.cdb
课设/v3/db/Verilog1.(4).cnf.hdb
课设/v3/db/Verilog1.(5).cnf.cdb
课设/v3/db/Verilog1.(5).cnf.hdb
课设/v3/db/Verilog1.(6).cnf.cdb
课设/v3/db/Verilog1.(6).cnf.hdb
课设/v3/db/Verilog1.(7).cnf.cdb
课设/v3/db/Verilog1.(7).cnf.hdb
课设/v3/db/Verilog1.(8).cnf.cdb
课设/v3/db/Verilog1.(8).cnf.hdb
课设/v3/db/Verilog1.asm.qmsg
课设/v3/db/Verilog1.asm_labs.ddb
课设/v3/db/Verilog1.cbx.xml
课设/v3/db/Verilog1.cmp.bpm
课设/v3/db/Verilog1.cmp.cdb
课设/v3/db/Verilog1.cmp.ecobp
课设/v3/db/Verilog1.cmp.hdb
课设/v3/db/Verilog1.cmp.kpt
课设/v3/db/Verilog1.cmp.logdb
课设/v3/db/Verilog1.cmp.rdb
课设/v3/db/Verilog1.cmp_merge.kpt
课设/v3/db/Verilog1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
课设/v3/db/Verilog1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
课设/v3/db/Verilog1.db_info
课设/v3/db/Verilog1.eco.cdb
课设/v3/db/Verilog1.eda.qmsg
课设/v3/db/Verilog1.eds_overflow
课设/v3/db/Verilog1.fit.qmsg
课设/v3/db/Verilog1.fnsim.cdb
课设/v3/db/Verilog1.fnsim.hdb
课设/v3/db/Verilog1.fnsim.qmsg
课设/v3/db/Verilog1.hier_info
课设/v3/db/Verilog1.hif
课设/v3/db/Verilog1.lpc.html
课设/v3/db/Verilog1.lpc.rdb
课设/v3/db/Verilog1.lpc.txt
课设/v3/db/Verilog1.map.bpm
课设/v3/db/Verilog1.map.cdb
课设/v3/db/Verilog1.map.ecobp
课设/v3/db/Verilog1.map.hdb
课设/v3/db/Verilog1.map.kpt
课设/v3/db/Verilog1.map.logdb
课设/v3/db/Verilog1.map.qmsg
课设/v3/db/Verilog1.map_bb.cdb
课设/v3/db/Verilog1.map_bb.hdb
课设/v3/db/Verilog1.map_bb.logdb
课设/v3/db/Verilog1.pre_map.cdb
课设/v3/db/Verilog1.pre_map.hdb
课设/v3/db/Verilog1.rtlv.hdb
课设/v3/db/Verilog1.rtlv_sg.cdb
课设/v3/db/Verilog1.rtlv_sg_swap.cdb
课设/v3/db/Verilog1.sgdiff.cdb
课设/v3/db/Verilog1.sgdiff.hdb
课设/v3/db/Verilog1.sim.cvwf
课设/v3/db/Verilog1.sim.hdb
课设/v3/db/Verilog1.sim.qmsg
课设/v3/db/Verilog1.sim.rdb
课设/v3/db/Verilog1.sld_design_entry.sci
课设/v3/db/Verilog1.sld_design_entry_dsc.sci
课设/v3/db/Verilog1.sta.qmsg
课设/v3/db/Verilog1.sta.rdb
课设/v3/db/Verilog1.sta_cmp.6_slow_1200mv_85c.tdb
课设/v3/db/Verilog1.syn_hier_info
课设/v3/db/Verilog1.tis_db_list.ddb
课设/v3/db/Verilog1.tiscmp.fast_1200mv_0c.ddb
课设/v3/db/Verilog1.tiscmp.slow_1200mv_0c.ddb
课设/v3/db/Verilog1.tiscmp.slow_1200mv_85c.ddb
课设/v3/db/Verilog1_global_asgn_op.abo
课设/v3/db/add_sub_unc.tdf
课设/v3/db/add_sub_vnc.tdf
课设/v3/db/alt_u_div_t2f.tdf
课设/v3/db/lpm_divide_8gm.tdf
课设/v3/db/lpm_divide_b8m.tdf
课设/v3/db/mux_7qc.tdf
课设/v3/db/mux_src.tdf
课设/v3/db/prev_cmp_Verilog1.asm.qmsg
课设/v3/db/prev_cmp_Verilog1.eda.qmsg
课设/v3/db/prev_cmp_Verilog1.fit.qmsg
课设/v3/db/prev_cmp_Verilog1.map.qmsg
课设/v3/db/prev_cmp_Verilog1.qmsg
课设/v3/db/prev_cmp_Verilog1.sim.qmsg
课设/v3/db/prev_cmp_Verilog1.sta.qmsg
课设/v3/db/sign_div_unsign_9kh.tdf
课设/v3/db/wed.wsf
课设/v3/incremental_db/
课设/v3/incremental_db/README
课设/v3/incremental_db/compiled_partitions/
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.atm
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.dfp
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.hdbx
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.kpt
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.logdb
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.rcf
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.atm
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.dpi
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.hdbx
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.kpt
课设/v3/simulation/
课设/v3/simulation/modelsim/
课设/v3/simulation/modelsim/Verilog1.sft
课设/v3/simulation/modelsim/Verilog1.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_0c_slow.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_0c_vhd_slow.sdo
课设/v3/simulation/modelsim/Verilog1_6_1200mv_85c_slow.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_85c_vhd_slow.sdo
课设/v3/simulation/modelsim/Verilog1_min_1200mv_0c_fast.vho
课设/v3/simulation/modelsim/Verilog1_min_1200mv_0c_vhd_fast.sdo
课设/v3/simulation/modelsim/Verilog1_modelsim.xrf
课设/v3/simulation/modelsim/Verilog1_vhd.sdo
课设/课设实验报告最终版3.doc
课设/课设答辩3.ppt
课设/v3/
课设/v3/Verilog1.asm.rpt
课设/v3/Verilog1.done
课设/v3/Verilog1.dpf
课设/v3/Verilog1.eda.rpt
课设/v3/Verilog1.fit.rpt
课设/v3/Verilog1.fit.summary
课设/v3/Verilog1.flow.rpt
课设/v3/Verilog1.map.rpt
课设/v3/Verilog1.map.smsg
课设/v3/Verilog1.map.summary
课设/v3/Verilog1.pin
课设/v3/Verilog1.qpf
课设/v3/Verilog1.qsf
课设/v3/Verilog1.qsf.bak
课设/v3/Verilog1.qws
课设/v3/Verilog1.sim.rpt
课设/v3/Verilog1.sof
课设/v3/Verilog1.sta.rpt
课设/v3/Verilog1.sta.summary
课设/v3/Verilog1.v
课设/v3/Verilog1.v.bak
课设/v3/Verilog1.vwf
课设/v3/Waveform1.vwf
课设/v3/db/
课设/v3/db/Verilog1.(0).cnf.cdb
课设/v3/db/Verilog1.(0).cnf.hdb
课设/v3/db/Verilog1.(1).cnf.cdb
课设/v3/db/Verilog1.(1).cnf.hdb
课设/v3/db/Verilog1.(2).cnf.cdb
课设/v3/db/Verilog1.(2).cnf.hdb
课设/v3/db/Verilog1.(3).cnf.cdb
课设/v3/db/Verilog1.(3).cnf.hdb
课设/v3/db/Verilog1.(4).cnf.cdb
课设/v3/db/Verilog1.(4).cnf.hdb
课设/v3/db/Verilog1.(5).cnf.cdb
课设/v3/db/Verilog1.(5).cnf.hdb
课设/v3/db/Verilog1.(6).cnf.cdb
课设/v3/db/Verilog1.(6).cnf.hdb
课设/v3/db/Verilog1.(7).cnf.cdb
课设/v3/db/Verilog1.(7).cnf.hdb
课设/v3/db/Verilog1.(8).cnf.cdb
课设/v3/db/Verilog1.(8).cnf.hdb
课设/v3/db/Verilog1.asm.qmsg
课设/v3/db/Verilog1.asm_labs.ddb
课设/v3/db/Verilog1.cbx.xml
课设/v3/db/Verilog1.cmp.bpm
课设/v3/db/Verilog1.cmp.cdb
课设/v3/db/Verilog1.cmp.ecobp
课设/v3/db/Verilog1.cmp.hdb
课设/v3/db/Verilog1.cmp.kpt
课设/v3/db/Verilog1.cmp.logdb
课设/v3/db/Verilog1.cmp.rdb
课设/v3/db/Verilog1.cmp_merge.kpt
课设/v3/db/Verilog1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
课设/v3/db/Verilog1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
课设/v3/db/Verilog1.db_info
课设/v3/db/Verilog1.eco.cdb
课设/v3/db/Verilog1.eda.qmsg
课设/v3/db/Verilog1.eds_overflow
课设/v3/db/Verilog1.fit.qmsg
课设/v3/db/Verilog1.fnsim.cdb
课设/v3/db/Verilog1.fnsim.hdb
课设/v3/db/Verilog1.fnsim.qmsg
课设/v3/db/Verilog1.hier_info
课设/v3/db/Verilog1.hif
课设/v3/db/Verilog1.lpc.html
课设/v3/db/Verilog1.lpc.rdb
课设/v3/db/Verilog1.lpc.txt
课设/v3/db/Verilog1.map.bpm
课设/v3/db/Verilog1.map.cdb
课设/v3/db/Verilog1.map.ecobp
课设/v3/db/Verilog1.map.hdb
课设/v3/db/Verilog1.map.kpt
课设/v3/db/Verilog1.map.logdb
课设/v3/db/Verilog1.map.qmsg
课设/v3/db/Verilog1.map_bb.cdb
课设/v3/db/Verilog1.map_bb.hdb
课设/v3/db/Verilog1.map_bb.logdb
课设/v3/db/Verilog1.pre_map.cdb
课设/v3/db/Verilog1.pre_map.hdb
课设/v3/db/Verilog1.rtlv.hdb
课设/v3/db/Verilog1.rtlv_sg.cdb
课设/v3/db/Verilog1.rtlv_sg_swap.cdb
课设/v3/db/Verilog1.sgdiff.cdb
课设/v3/db/Verilog1.sgdiff.hdb
课设/v3/db/Verilog1.sim.cvwf
课设/v3/db/Verilog1.sim.hdb
课设/v3/db/Verilog1.sim.qmsg
课设/v3/db/Verilog1.sim.rdb
课设/v3/db/Verilog1.sld_design_entry.sci
课设/v3/db/Verilog1.sld_design_entry_dsc.sci
课设/v3/db/Verilog1.sta.qmsg
课设/v3/db/Verilog1.sta.rdb
课设/v3/db/Verilog1.sta_cmp.6_slow_1200mv_85c.tdb
课设/v3/db/Verilog1.syn_hier_info
课设/v3/db/Verilog1.tis_db_list.ddb
课设/v3/db/Verilog1.tiscmp.fast_1200mv_0c.ddb
课设/v3/db/Verilog1.tiscmp.slow_1200mv_0c.ddb
课设/v3/db/Verilog1.tiscmp.slow_1200mv_85c.ddb
课设/v3/db/Verilog1_global_asgn_op.abo
课设/v3/db/add_sub_unc.tdf
课设/v3/db/add_sub_vnc.tdf
课设/v3/db/alt_u_div_t2f.tdf
课设/v3/db/lpm_divide_8gm.tdf
课设/v3/db/lpm_divide_b8m.tdf
课设/v3/db/mux_7qc.tdf
课设/v3/db/mux_src.tdf
课设/v3/db/prev_cmp_Verilog1.asm.qmsg
课设/v3/db/prev_cmp_Verilog1.eda.qmsg
课设/v3/db/prev_cmp_Verilog1.fit.qmsg
课设/v3/db/prev_cmp_Verilog1.map.qmsg
课设/v3/db/prev_cmp_Verilog1.qmsg
课设/v3/db/prev_cmp_Verilog1.sim.qmsg
课设/v3/db/prev_cmp_Verilog1.sta.qmsg
课设/v3/db/sign_div_unsign_9kh.tdf
课设/v3/db/wed.wsf
课设/v3/incremental_db/
课设/v3/incremental_db/README
课设/v3/incremental_db/compiled_partitions/
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.atm
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.dfp
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.hdbx
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.kpt
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.logdb
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.cmp.rcf
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.atm
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.dpi
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.hdbx
课设/v3/incremental_db/compiled_partitions/Verilog1.root_partition.map.kpt
课设/v3/simulation/
课设/v3/simulation/modelsim/
课设/v3/simulation/modelsim/Verilog1.sft
课设/v3/simulation/modelsim/Verilog1.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_0c_slow.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_0c_vhd_slow.sdo
课设/v3/simulation/modelsim/Verilog1_6_1200mv_85c_slow.vho
课设/v3/simulation/modelsim/Verilog1_6_1200mv_85c_vhd_slow.sdo
课设/v3/simulation/modelsim/Verilog1_min_1200mv_0c_fast.vho
课设/v3/simulation/modelsim/Verilog1_min_1200mv_0c_vhd_fast.sdo
课设/v3/simulation/modelsim/Verilog1_modelsim.xrf
课设/v3/simulation/modelsim/Verilog1_vhd.sdo
课设/课设实验报告最终版3.doc
课设/课设答辩3.ppt
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