This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs.　The component reads　and writes to user logic over a parallel interface.　It was designed using Quartus II, version 11.1.