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文件名称:USB3_a3p1000_9.1__

  • 所属分类：
    Other systems
  • 标签属性：
  • 上传时间：
    2015-09-26
  • 文件大小：
    8.82mb
  • 已下载：
    0次
  • 提 供 者：
    j*****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

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8bit10bit编解码、SPI解串、BAT656接受源码，并通过USB3.0 传送至PC机。经测试actel fpga 时钟频率100M可以满足320MB/s的传输速率-8bit10bit encoding and decoding, SPI solution string, BAT656 accept the source code, and through USB3.0 to PC. After testing the FPGA Actel clock frequency 100M can meet the transmission rate of 320MB/s
(系统自动生成,下载前可以参看下载内容)

下载文件列表

USB3_a3p1000_9.1/aaa.dpz
USB3_a3p1000_9.1/component/work/aaa/aaa.cxf
USB3_a3p1000_9.1/component/work/aaa/aaa.sdb
USB3_a3p1000_9.1/constraint/1.pdc
USB3_a3p1000_9.1/constraint/data/1.pdc.ce
USB3_a3p1000_9.1/constraint/data/usb3_top_32bit_pin.pdc.ce
USB3_a3p1000_9.1/constraint/slaveFIFO2b_loopback_1_sdc.sdc
USB3_a3p1000_9.1/constraint/usb3_top_32bit_pin.pdc
USB3_a3p1000_9.1/constraint/usb3_top_32bit_pin_20140517.rar
USB3_a3p1000_9.1/designer/impl2/11111111/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/11111111/11111111.log
USB3_a3p1000_9.1/designer/impl2/11111111/11111111.pro
USB3_a3p1000_9.1/designer/impl2/11111111/projectData/slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
USB3_a3p1000_9.1/designer/impl2/designer.log
USB3_a3p1000_9.1/designer/impl2/fifo_money.ide_des
USB3_a3p1000_9.1/designer/impl2/pll_25_to_100.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_fpga_top.ide_des
USB3_a3p1000_9.1/designer/impl2/slavefifo2b_fpga_top_tb.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback.tcl
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1.adb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1.dtf/verify.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1.pdb.depends
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_fp/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_fp/projectData/slaveFIFO2b_loopback_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_fp/slaveFIFO2b_loopback_1.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_fp/slaveFIFO2b_loopback_1.pro
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1.adb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1.dtf/verify.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1.pdb.depends
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1_fp/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1_fp/projectData/slaveFIFO2b_loopback_1_synthesis_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1_fp/slaveFIFO2b_loopback_1_synthesis_1.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback_1_synthesis_1_fp/slaveFIFO2b_loopback_1_synthesis_1.pro
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis.adb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis.dtf/verify.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis.pdb.depends
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1.adb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1.dtf/verify.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb.depends
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1_fp/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1_fp/projectData/slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1_fp/slaveFIFO2b_loopback__all_in_1_synthesis_1.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_1_fp/slaveFIFO2b_loopback__all_in_1_synthesis_1.pro
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2.adb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2.dtf/verify.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2.ide_des
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2.pdb.depends
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2_fp/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2_fp/projectData/slaveFIFO2b_loopback__all_in_1_synthesis_2.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2_fp/slaveFIFO2b_loopback__all_in_1_synthesis_2.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_2_fp/slaveFIFO2b_loopback__all_in_1_synthesis_2.pro
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_fp/$$FlashPro_66705.L$$
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_fp/projectData/slaveFIFO2b_loopback__all_in_1_synthesis.pdb
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_1_synthesis_fp/slaveFIFO2b_loopback__all_in_1_synthesis.log
USB3_a3p1000_9.1/designer/impl2/slaveFIFO2b_loopback__all_in_

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