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文件名称:cpu

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  • 上传时间:
    2016-03-30
  • 文件大小:
    12.81mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

CPU设计,本科大作业,主要是CPU的工作原理及与打印机相结合-CPU design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpu/2.bit
cpu/ALU.bld
cpu/ALU.cmd_log
cpu/ALU.lso
cpu/ALU.ncd
cpu/ALU.ngc
cpu/ALU.ngd
cpu/ALU.ngr
cpu/ALU.pad
cpu/ALU.par
cpu/ALU.pcf
cpu/ALU.prj
cpu/ALU.ptwx
cpu/ALU.spl
cpu/ALU.stx
cpu/ALU.sym
cpu/ALU.syr
cpu/ALU.twr
cpu/ALU.twx
cpu/ALU.unroutes
cpu/alu.vhd
cpu/ALU.vhi
cpu/ALU.xpi
cpu/ALU.xst
cpu/ALU_envsettings.html
cpu/ALU_guide.ncd
cpu/ALU_map.map
cpu/ALU_map.mrp
cpu/ALU_map.ncd
cpu/ALU_map.ngm
cpu/ALU_map.xrpt
cpu/ALU_ngdbuild.xrpt
cpu/ALU_pad.csv
cpu/ALU_pad.txt
cpu/ALU_par.xrpt
cpu/ALU_summary.html
cpu/ALU_summary.xml
cpu/ALU_usage.xml
cpu/ALU_xst.xrpt
cpu/BR.cmd_log
cpu/BR.spl
cpu/BR.sym
cpu/br.vhd
cpu/BR_summary.html
cpu/cheng.coe
cpu/cpu.gise
cpu/cpu.xise
cpu/CPU_04012145 04012113_.doc
cpu/CU.cmd_log
cpu/CU.spl
cpu/CU.sym
cpu/cu.vhd
cpu/DR.cmd_log
cpu/DR.spl
cpu/DR.sym
cpu/dr.vhd
cpu/fangzhen.bgn
cpu/fangzhen.bit
cpu/fangzhen.bld
cpu/fangzhen.cmd_log
cpu/fangzhen.drc
cpu/fangzhen.jhd
cpu/fangzhen.lso
cpu/fangzhen.ncd
cpu/fangzhen.ngc
cpu/fangzhen.ngd
cpu/fangzhen.ngr
cpu/fangzhen.pad
cpu/fangzhen.par
cpu/fangzhen.pcf
cpu/fangzhen.prj
cpu/fangzhen.ptwx
cpu/fangzhen.sch
cpu/fangzhen.schbak
cpu/fangzhen.stx
cpu/fangzhen.syr
cpu/fangzhen.twr
cpu/fangzhen.twx
cpu/fangzhen.unroutes
cpu/fangzhen.ut
cpu/fangzhen.vhd
cpu/fangzhen.vhf
cpu/fangzhen.xpi
cpu/fangzhen.xst
cpu/fangzhengai.vhd
cpu/fangzhen_bitgen.xwbt
cpu/fangzhen_drc.vhf
cpu/fangzhen_envsettings.html
cpu/fangzhen_fangzhen_sch_tb_beh.prj
cpu/fangzhen_fangzhen_sch_tb_isim_beh.exe
cpu/fangzhen_fangzhen_sch_tb_isim_beh.wdb
cpu/fangzhen_fangzhen_sch_tb_stx_beh.prj
cpu/fangzhen_guide.ncd
cpu/fangzhen_map.map
cpu/fangzhen_map.mrp
cpu/fangzhen_map.ncd
cpu/fangzhen_map.ngm
cpu/fangzhen_map.xrpt
cpu/fangzhen_ngdbuild.xrpt
cpu/fangzhen_pad.csv
cpu/fangzhen_pad.txt
cpu/fangzhen_par.xrpt
cpu/fangzhen_summary.html
cpu/fangzhen_summary.xml
cpu/fangzhen_usage.xml
cpu/fangzhen_xst.xrpt
cpu/fuse.log
cpu/fuse.xmsgs
cpu/fuseRelaunch.cmd
cpu/fwqfwq.vhd
cpu/ipcore_dir/blk_mem_gen_ds512.pdf
cpu/ipcore_dir/blk_mem_gen_v6_3_readme.txt
cpu/ipcore_dir/coregen.cgp
cpu/ipcore_dir/coregen.log
cpu/ipcore_dir/create_RAM.tcl
cpu/ipcore_dir/create_ROM.tcl
cpu/ipcore_dir/edit_RAM.tcl
cpu/ipcore_dir/edit_ROM.tcl
cpu/ipcore_dir/gen_RAM.tcl
cpu/ipcore_dir/gen_ROM.tcl
cpu/ipcore_dir/RAM/example_design/bmg_wrapper.vhd
cpu/ipcore_dir/RAM/example_design/RAM_top.ucf
cpu/ipcore_dir/RAM/example_design/RAM_top.vhd
cpu/ipcore_dir/RAM/example_design/RAM_top.xdc
cpu/ipcore_dir/RAM/implement/implement.bat
cpu/ipcore_dir/RAM/implement/implement.sh
cpu/ipcore_dir/RAM/implement/planAhead_rdn.bat
cpu/ipcore_dir/RAM/implement/planAhead_rdn.sh
cpu/ipcore_dir/RAM/implement/planAhead_rdn.tcl
cpu/ipcore_dir/RAM/implement/xst.prj
cpu/ipcore_dir/RAM/implement/xst.scr
cpu/ipcore_dir/RAM/simulation/addr_gen.vhd
cpu/ipcore_dir/RAM/simulation/bmg_stim_gen.vhd
cpu/ipcore_dir/RAM/simulation/bmg_tb_pkg.vhd
cpu/ipcore_dir/RAM/simulation/bmg_tb_synth.vhd
cpu/ipcore_dir/RAM/simulation/bmg_tb_top.vhd
cpu/ipcore_dir/RAM/simulation/checker.vhd
cpu/ipcore_dir/RAM/simulation/data_gen.vhd
cpu/ipcore_dir/RAM/simulation/functional/isim_tcl_cmds.tcl
cpu/ipcore_dir/RAM/simulation/functional/simulate_isim.bat
cpu/ipcore_dir/RAM/simulation/functional/simulate_mti.do
cpu/ipcore_dir/RAM/simulation/functional/simulate_ncsim.sh
cpu/ipcore_dir/RAM/simulation/functional/wave_mti.do
cpu/ipcore_dir/RAM/simulation/functional/wave_ncsim.sv
cpu/ipcore_dir/RAM/simulation/random.vhd
cpu/ipcore_dir/RAM/simulation/timing/isim_tcl_cmds.tcl
cpu/ipcore_dir/RAM/simulation/timing/simulate_isim.bat
cpu/ipcore_dir/RAM/simulation/timing/simulate_mti.do
cpu/ipcore_dir/RAM/simulation/timing/simulate_ncsim.sh
cpu/ipcore_dir/RAM/simulation/timing/wave_mti.do
cpu/ipcore_dir/RAM/simulation/timing/wave_ncsim.sv
cpu/ipcore_dir/RAM.asy
cpu/ipcore_dir/RAM.gise
cpu/ipcore_dir/RAM.mif
cpu/ipcore_dir/RAM.ncf
cpu/ipcore_dir/RAM.ngc
cpu/ipcore_dir/RAM.sym
cpu/ipcore_dir/RAM.vhd
cpu/ipcore_dir/RAM.vho
cpu/ipcore_dir/RAM.xco
cpu/ipcore_dir/RAM.xise
cpu/ipcore_dir/RAM_flist.txt
cpu/ipcore_dir/RAM_xmdf.tcl
cpu/ipcore_dir/ROM/example_design/bmg_wrapper.vhd
cpu/ipcore_dir/ROM/example_design/ROM_top.ucf
cpu/ipcore_dir/ROM/example_design/ROM_top.vhd
cpu/ipcore_dir/ROM/example_design/ROM_top.xdc
cpu/ipcore_dir/ROM/implement/implement.bat
cpu/ipcore_dir/ROM/implement/implement.sh
cpu/ipcore_dir/ROM/implement/planAhead_rdn.bat
cpu/ipcore_dir/ROM/implement/planAhead_rdn.sh
cpu/ipcore_dir/ROM/implement/planAhead_rdn.tcl
cpu/ipcore_dir/ROM/implement/xst.prj
cpu/ipcore_dir/ROM/implement/xst.scr
cpu/ipcore_dir/ROM/simulation/addr_gen.vhd
cpu/ipcore_dir/ROM/simulation/bmg_stim_gen.vhd
cpu/ipcore_dir/ROM/simulation/bmg_tb_pkg.vhd
cpu/ipcore_dir/ROM/simulation/bmg_tb_synth.vhd
cpu/ipcore_dir/ROM/simulation/bmg_tb_top.vhd
cpu/ipcore_dir/ROM/simulation/functional/isim_tcl_cmds.tcl
cpu/ipcore_dir/ROM/simulation/functional/simulate_isim.bat
cpu/ipcore_dir/ROM/simulation/functional/simulate_mti.do
cpu/ipcore_dir/ROM/simulation/functional/simulate_ncsim.sh
cpu/ipcore_dir/ROM/simulation/functional/wave_mti.do
cpu/ipcore_dir/ROM/simulation/functional/wave_ncsim.sv
cpu/ipcore_dir/ROM/simulation/random.vhd
cp

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