文件名称:lab03-.tar
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- 上传时间:2016-05-25
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vhdl about 3 stage control block of cpu-vhdl control block of the 3 stage cpu(FSM)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
GROUP01_LAB03/
GROUP01_LAB03/VHDLSIM/
GROUP01_LAB03/VHDLSIM/registerfile.vhd
GROUP01_LAB03/VHDLSIM/lab3_1_3.ps
GROUP01_LAB03/VHDLSIM/window_register_file.vhd
GROUP01_LAB03/VHDLSIM/tb_windowregisterfile.vhd
GROUP01_LAB03/VHDLSIM/lab3_1_1.ps
GROUP01_LAB03/SYN/
GROUP01_LAB03/SYN/register_file3_1_2.scr
GROUP01_LAB03/SYN/timing_report3_1_2.txt
GROUP01_LAB03/SYN/timing_reportnop3_1_6.txt
GROUP01_LAB03/SYN/3_1_2.vhdl
GROUP01_LAB03/SYN/sipisoalu_pw.scr
GROUP01_LAB03/SYN/timing_report3_1_4.txt
GROUP01_LAB03/SYN/net_power_reportnop3_1_6.txt
GROUP01_LAB03/SYN/lab3_1_4.vhdl
GROUP01_LAB03/SYN/timing_reportmax3_!_6.txt
GROUP01_LAB03/SYN/timing_reportop3_1_6.txt
GROUP01_LAB03/SYN/power_reportop3_1_6.txt
GROUP01_LAB03/SYN/power_reportnop3_1_6.txt
GROUP01_LAB03/SYN/cell_power_reportnop3_1_6.txt
GROUP01_LAB03/VHDLSIM/
GROUP01_LAB03/VHDLSIM/registerfile.vhd
GROUP01_LAB03/VHDLSIM/lab3_1_3.ps
GROUP01_LAB03/VHDLSIM/window_register_file.vhd
GROUP01_LAB03/VHDLSIM/tb_windowregisterfile.vhd
GROUP01_LAB03/VHDLSIM/lab3_1_1.ps
GROUP01_LAB03/SYN/
GROUP01_LAB03/SYN/register_file3_1_2.scr
GROUP01_LAB03/SYN/timing_report3_1_2.txt
GROUP01_LAB03/SYN/timing_reportnop3_1_6.txt
GROUP01_LAB03/SYN/3_1_2.vhdl
GROUP01_LAB03/SYN/sipisoalu_pw.scr
GROUP01_LAB03/SYN/timing_report3_1_4.txt
GROUP01_LAB03/SYN/net_power_reportnop3_1_6.txt
GROUP01_LAB03/SYN/lab3_1_4.vhdl
GROUP01_LAB03/SYN/timing_reportmax3_!_6.txt
GROUP01_LAB03/SYN/timing_reportop3_1_6.txt
GROUP01_LAB03/SYN/power_reportop3_1_6.txt
GROUP01_LAB03/SYN/power_reportnop3_1_6.txt
GROUP01_LAB03/SYN/cell_power_reportnop3_1_6.txt
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