文件名称:sdram_top
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- 上传时间：2017-01-22
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文件大小：200.39kb
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使用FPGA实现SDRAM逻辑控制器，适用于各种型号的FPGA-SDRAM control by verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sdram_top/
sdram_top/SDRAM_test.v
sdram_top/fifo_test.bsf
sdram_top/fifo_test.cmp
sdram_top/fifo_test.inc
sdram_top/fifo_test.qip
sdram_top/fifo_test.v
sdram_top/fifo_test_bb.v
sdram_top/fifo_test_inst.v
sdram_top/fifo_test_wave0.jpg
sdram_top/fifo_test_wave1.jpg
sdram_top/in_buffer_test.v
sdram_top/out_buffer_test.v
sdram_top/sdram/
sdram_top/sdram/sdram_cmd.v
sdram_top/sdram/sdram_ctrl.v
sdram_top/sdram/sdram_para.v
sdram_top/sdram/sdram_top.v
sdram_top/sdram/sdram_wr_data.v
sdram_top/sdram/sdram_wr_data.v.bak
sdram_top/sdram_ctr.v
sdram_top/sdram_ctr.v.bak
sdram_top/sdram_test_para.v
sdram_top/SDRAM_test.v
sdram_top/fifo_test.bsf
sdram_top/fifo_test.cmp
sdram_top/fifo_test.inc
sdram_top/fifo_test.qip
sdram_top/fifo_test.v
sdram_top/fifo_test_bb.v
sdram_top/fifo_test_inst.v
sdram_top/fifo_test_wave0.jpg
sdram_top/fifo_test_wave1.jpg
sdram_top/in_buffer_test.v
sdram_top/out_buffer_test.v
sdram_top/sdram/
sdram_top/sdram/sdram_cmd.v
sdram_top/sdram/sdram_ctrl.v
sdram_top/sdram/sdram_para.v
sdram_top/sdram/sdram_top.v
sdram_top/sdram/sdram_wr_data.v
sdram_top/sdram/sdram_wr_data.v.bak
sdram_top/sdram_ctr.v
sdram_top/sdram_ctr.v.bak
sdram_top/sdram_test_para.v
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