General Descr iption
These octal bus transceivers are designed for asynchronous
two-way communication between data buses. The
control function implementation minimizes external timing
requirements.
The device allows data transmission from the A Bus to the
B Bus or from the B Bus to the A Bus depending upon the
logic level at the direction control (DIR) input. The enable
input (G) can be used to disable the device so that the
buses are effectively isolated