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文件名称:gpio

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    637.58kb
  • 已下载：
    1次
  • 提 供 者：
    aste****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一个可综合的verilog描述的GPIO代码。-A GPIO design in verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

gpio/bench/CVS/Entries
gpio/bench/CVS/Repository
gpio/bench/CVS/Root
gpio/bench/verilog/clkrst.v
gpio/bench/verilog/CVS/Entries
gpio/bench/verilog/CVS/Repository
gpio/bench/verilog/CVS/Root
gpio/bench/verilog/gpio_mon.v
gpio/bench/verilog/gpio_testbench.v
gpio/bench/verilog/tb_defines.v
gpio/bench/verilog/tb_tasks.v
gpio/bench/verilog/timescale.v
gpio/bench/verilog/wb_master.v
gpio/bench/VHDL/CVS/Entries
gpio/bench/VHDL/CVS/Repository
gpio/bench/VHDL/CVS/Root
gpio/CVS/Entries
gpio/CVS/Repository
gpio/CVS/Root
gpio/doc/CVS/Entries
gpio/doc/CVS/Repository
gpio/doc/CVS/Root
gpio/doc/gpio_spec.pdf
gpio/doc/src/CVS/Entries
gpio/doc/src/CVS/Repository
gpio/doc/src/CVS/Root
gpio/doc/src/gpio_spec.doc
gpio/fv/CVS/Entries
gpio/fv/CVS/Repository
gpio/fv/CVS/Root
gpio/gpio_spec.pdf
gpio/lint/bin/CVS/Entries
gpio/lint/bin/CVS/Repository
gpio/lint/bin/CVS/Root
gpio/lint/CVS/Entries
gpio/lint/CVS/Repository
gpio/lint/CVS/Root
gpio/lint/log/CVS/Entries
gpio/lint/log/CVS/Repository
gpio/lint/log/CVS/Root
gpio/lint/out/CVS/Entries
gpio/lint/out/CVS/Repository
gpio/lint/out/CVS/Root
gpio/lint/run/CVS/Entries
gpio/lint/run/CVS/Repository
gpio/lint/run/CVS/Root
gpio/rtl/CVS/Entries
gpio/rtl/CVS/Repository
gpio/rtl/CVS/Root
gpio/rtl/verilog/CVS/Entries
gpio/rtl/verilog/CVS/Repository
gpio/rtl/verilog/CVS/Root
gpio/rtl/verilog/gpio_defines.v
gpio/rtl/verilog/gpio_top.v
gpio/rtl/VHDL/CVS/Entries
gpio/rtl/VHDL/CVS/Repository
gpio/rtl/VHDL/CVS/Root
gpio/sim/CVS/Entries
gpio/sim/CVS/Repository
gpio/sim/CVS/Root
gpio/sim/gate_sim/bin/CVS/Entries
gpio/sim/gate_sim/bin/CVS/Repository
gpio/sim/gate_sim/bin/CVS/Root
gpio/sim/gate_sim/CVS/Entries
gpio/sim/gate_sim/CVS/Repository
gpio/sim/gate_sim/CVS/Root
gpio/sim/gate_sim/log/CVS/Entries
gpio/sim/gate_sim/log/CVS/Repository
gpio/sim/gate_sim/log/CVS/Root
gpio/sim/gate_sim/out/CVS/Entries
gpio/sim/gate_sim/out/CVS/Repository
gpio/sim/gate_sim/out/CVS/Root
gpio/sim/gate_sim/run/CVS/Entries
gpio/sim/gate_sim/run/CVS/Repository
gpio/sim/gate_sim/run/CVS/Root
gpio/sim/gate_sim/src/CVS/Entries
gpio/sim/gate_sim/src/CVS/Repository
gpio/sim/gate_sim/src/CVS/Root
gpio/sim/rtl_sim/bin/cds.lib
gpio/sim/rtl_sim/bin/CVS/Entries
gpio/sim/rtl_sim/bin/CVS/Repository
gpio/sim/rtl_sim/bin/CVS/Root
gpio/sim/rtl_sim/bin/hdl.var
gpio/sim/rtl_sim/bin/INCA_libs/CVS/Entries
gpio/sim/rtl_sim/bin/INCA_libs/CVS/Repository
gpio/sim/rtl_sim/bin/INCA_libs/CVS/Root
gpio/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Entries
gpio/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Repository
gpio/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Root
gpio/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
gpio/sim/rtl_sim/bin/rtl_file_list
gpio/sim/rtl_sim/bin/sim.sh
gpio/sim/rtl_sim/bin/sim_file_list
gpio/sim/rtl_sim/CVS/Entries
gpio/sim/rtl_sim/CVS/Repository
gpio/sim/rtl_sim/CVS/Root
gpio/sim/rtl_sim/log/CVS/Entries
gpio/sim/rtl_sim/log/CVS/Repository
gpio/sim/rtl_sim/log/CVS/Root
gpio/sim/rtl_sim/log/ncelab.log
gpio/sim/rtl_sim/log/ncsim.log
gpio/sim/rtl_sim/log/ncvlog.log
gpio/sim/rtl_sim/out/CVS/Entries
gpio/sim/rtl_sim/out/CVS/Repository
gpio/sim/rtl_sim/out/CVS/Root
gpio/sim/rtl_sim/run/CVS/Entries
gpio/sim/rtl_sim/run/CVS/Repository
gpio/sim/rtl_sim/run/CVS/Root
gpio/sim/rtl_sim/run/ncelab.args
gpio/sim/rtl_sim/run/ncsim.args
gpio/sim/rtl_sim/run/ncsim.tcl
gpio/sim/rtl_sim/run/ncvlog.args
gpio/sim/rtl_sim/run/run_sim
gpio/sim/rtl_sim/run/run_sim_gpio
gpio/sim/rtl_sim/src/CVS/Entries
gpio/sim/rtl_sim/src/CVS/Repository
gpio/sim/rtl_sim/src/CVS/Root
gpio/syn/bin/cons_art_umc18.inc
gpio/syn/bin/cons_vs_umc18.inc
gpio/syn/bin/CVS/Entries
gpio/syn/bin/CVS/Repository
gpio/syn/bin/CVS/Root
gpio/syn/bin/read_design.inc
gpio/syn/bin/reports.inc
gpio/syn/bin/save_design.inc
gpio/syn/bin/select_tech.inc
gpio/syn/bin/set_env.inc
gpio/syn/bin/tech_art_umc18.inc
gpio/syn/bin/tech_vs_umc18.inc
gpio/syn/bin/top_gpio.scr
gpio/syn/CVS/Entries
gpio/syn/CVS/Repository
gpio/syn/CVS/Root
gpio/syn/log/CVS/Entries
gpio/syn/log/CVS/Repository
gpio/syn/log/CVS/Root
gpio/syn/out/CVS/Entries
gpio/syn/out/CVS/Repository
gpio/syn/out/CVS/Root
gpio/syn/run/CVS/Entries
gpio/syn/run/CVS/Repository
gpio/syn/run/CVS/Root
gpio/syn/run/dodesign
gpio/syn/src/CVS/Entries
gpio/syn/src/CVS/Repository
gpio/syn/src/CVS/Root
gpio/sim/rtl_sim/bin/INCA_libs/worklib/CVS
gpio/sim/rtl_sim/bin/INCA_libs/CVS
gpio/sim/rtl_sim/bin/INCA_libs/worklib
gpio/sim/gate_sim/bin/CVS
gpio/sim/gate_sim/log/CVS
gpio/sim/gate_sim/out/CVS
gpio/sim/gate_sim/run/CVS
gpio/sim/gate_sim/src/CVS
gpio/sim/rtl_sim/bin/CVS
gpio/sim/rtl_sim/bin/INCA_libs
gpio/sim/rtl_sim/log/CVS
gpio/sim/rtl_sim/out/CVS
gpio/sim/rtl_sim/run/CVS
gpio/sim/rtl_sim/src/CVS
gpio/bench/verilog/CVS
gpio/bench/VHDL/CVS
gpio/doc/src/CVS
gpio/lint/bin/CVS
gpio/lint/log/CVS
gpio/lint/out/CVS
gpio/lint/run/CVS
gpio/rtl/verilog/CVS
gpio/rtl/VHDL/CVS
gpio/sim/gate_sim/bin
gpio/sim/gate_sim/CVS
gpio/sim/gate_sim/log
gpio/sim/gate_sim/out
gpio/sim/gate_sim/run
gpio/sim/gate_sim/src
gpio/sim/rtl_sim/bin
gpio/sim/rtl_sim/CVS
gpio/sim/rtl_sim/log
gpio/sim/rtl_sim/out
gpio/sim/rtl_sim/run
gpio/sim/rtl_sim/src
gpio/syn/bin/CVS
gpio/syn/log/CVS
gpio/syn/out/CVS
gpio/syn/run/CVS
gpi

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