搜索资源列表
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
rs232
- 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
uart
- verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
DA
- Verilog HDL 写的１２位串口ＤＡ转换程序-Written in Verilog HDL conversion process 12-bit serial DA
uartverilog
- 用verilog语言编写uart程序。模拟串口时序进行收发数据操作。-verilog uart
Verilog
- 串口测试程序，用于单片机的串口发送接收数据测试用，-Serial port test program for the microcontroller serial port test sending and receiving data,
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
r232
- verilog下fpga串口，波特率115200，与PC通信-Under verilog fpga serial port, baud rate 115200, and PC communication
UART_DMA
- 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
Verilog-communication-source-code.RAR
- 基于Verilog的串口通信源码 ，实现串口通信功能-Verilog source code based on serial communication
UART_verilog
- 带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequ
Verilog-uart
- Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
Uart
- fpga verilog语言，写的串口通讯，经测试完全没有问题-fpga verilog uart communication
verilog-spi
- verilog 写的串口通信代码 code-verilog 写的串口通信代码
UART
- verilog写的串口程序，其功能完全最正确，带工程文件-verilog to write the serial program, its function is completely the right, with the project file
FPGA_serial(verilog)
- 采用verilog语言编写的关于串口通信的程序，可以参考，希望有所帮助。-Verilog language on the serial communication program can help.
01-The-basis-of-routine-verilog
- 是alter公司开发板上的，一些基础例程，包括串口、LED灯，计数器等等。-Alter development board, some basic routines, including the serial port, LED lights, counters, etc..
verilog
- verilog hdl 写的一个串口程序，编译仿真都已经通过-the verilog hdl write a serial program, compile simulation have passed