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Max232ForHLD3(20040913)(OK)
- 基于fpga和xinlinx ise的串行通信vhdl程序,希望对你有所帮助!-xinlinx and ideally serial communications VHDL process, and I hope to help you!
baud
- vhdl 很好用于串行通信. 三个模快,发生时钟,发送和 接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
I2C_IPcore_VHDL
- 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核,可直接编译运行-I2C serial data communication protocol to VHDL hardware descr iption language of the IP core can be directly translated Operation
s2p
- 用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
edaeda
- 完整的串行通信电路vhdl代码,已经通过quartus4.0编译-complete serial communication circuit VHDL code, the compiler has passed quartus4.0
UART(FPGA)
- 基于FPGA的串行通信UART控制器,采用VHDL语言编写,包含多个子模块。 在ISE或FPGA的其它开发环境下新建一个工程,然后将文档中的各个模块程序添加进去,即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new
produce
- vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation
multi8x8
- 节约资源型 8位*8位 运算VHDL代码,采用串行运算,8 个时钟周期完成一次运算。QUARTUS下已验证-resource conservation-8 * 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test
rs232_send
- rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
95108325
- 通过CPLD实现串行通信之VHDL语言,好看易懂-through CPLD serial communications VHDL, pretty easy to understand
AsynCommCtrl
- 基于VHDL的串行异步通信电路的设计 包括串行发送器,异步接收器,以及控制器 vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
8b10b_Encoder
- 应用VHDL设计的8b10b 编码器,对串行数据的高速传输有用。-application VHDL design 8b10b encoding device to the high-speed serial data transmission useful.
8b10b_Decoder
- 应用VHDL设计的8b10b解码器源文件,实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
VHDL_UART
- VHDL语言的UART串行接口芯片程序,仅供学习使用-VHDL UART serial interface chip procedure is for learning
control9851
- AD9851的vhdl串行控制程序(9851系统时钟内部指定)-AD9851 vhdl the serial control procedures (9851 designated internal system clock)
uart766
- ---实现的部分VHDL 程序如下。 --- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 down
changyongmokuai
- 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
用FPGA实现UART
- 用fpga实现异步串行通信。通过串口助手接收与发送(Implementation of serial communication with FPGA)
uart
- VHDL实现串口转换的代码,串行通信的发送器有五个状态:--1.X_IDLE(空闲)状态 : 当UART被复位后,状态机将立刻进入这一状态,在这个状态下, -- 状态机一直等待发送命令XMIT_CMD,当接收到发送命令后,状态机进入X_START状态,准备发送起始位信号 --2.X_START状态 : 在这个状态下,UART发送一个位时间宽度的逻辑'0',信号至TXD,即 -- 起始位,紧接着状态机进入X_SHIFT状态,发一位数据 --3.X_WAIT状态 : 当状态机处于这一个状态时
counter_displayer
- 基于fpga的vhdl数码管显示模块。已经译码,采用串行数据。(number displar base on vhdl)