搜索资源列表
ps
- VHDL语言编写的串并转换模块的源代码,用来将并行输入数据转换为串行数据输出-code for the transform of ps
SDHAnalysis
- 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码,共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
PiSo
- 8位并行输入的数转换成串行输出,是基于高级硬件编程语言VHDL编写的。-8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.
REACH
- 基于VHDL的异步串行通信电路设计 随着电子技术的发展,现场可编程门阵列FPGA和复杂可编程逻辑器件CPLD的出现,使得电子系统的设计者利用与器件相应的电子CAD软件,在实验室里就可以设计自己的专用集成电路ASIC器件。这种可编程ASIC不仅使设计的产品-VHDL-based asynchronous serial communication circuit design with the advent of electronic technology, field programmable g
rei2c
- 用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。-Quartusii prepared using VHDL platform to read the serial EEPROM configuration procedures.
VHDL_CPLD_serial
- 基于VHDL语言的一个新型串行数字通信模块。-Based on the VHDL language, a new serial digital communication module.
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计(串行式)-VHDL realization of finite impulse response filter design (Serial)
traffic
- 接口如下所示:clk:时钟输入端,此信号是串行扫描的同步信号; data_control[7..0]:8个分别控制数码管显示的输入信号; led_addr[7..0]:对8个数码管进行串行扫描的输出控制信号; seg7_data[6..0]驱动7段数码管各显示段的输出信号; -VHDL programing
fir8
- 用verilog编写的8阶串行fir滤波器-verilog vhdl fir
FPGA
- FPGA和单片机串行通信接口的实现,VHDL的源代码。-And single-chip FPGA realization of serial communication interface, VHDL source code.
Sim_SDAIN
- 并行数据转换串行数据发生VHDL程序,需要的同志可以看看是否可以用 自己写的-Serial data in parallel data conversion process occurred in VHDL, the comrades need to see if it can be written in their own
yiwei2
- 16位并行数据转换成串行数据,适用于FPGA与单片几之间的通信问题 (VHDL 编程)-FPGA VHDL
uart
- 异步串行接口设计 vhdl设计 fpga下载模拟-this is a vhdl programm
tongxunjiekou
- 基于VHDL语言,实现串行通讯接口功能的主程序-The use of VHDL language implementation of the serial communication interface program
uart_VHDL
- 基于VHDL的异步串行通信电路uart的设计-VHDL-based asynchronous serial communication circuit design uart
FPGA_RS232
- 为增加系统稳定性,减小电路板面积,提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性,可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
FIRFIR1
- 基于FPGA的FIR串行滤波器设计与实现,本文运用VHDL编写-FPGA-based FIR filter design and implementation of the serial, the paper prepared by the use of VHDL
zy4668_ybcxjk
- 本源码实现的功能是用VHDL编写异步串行接口设计-The source VHDL implementation of the function is the preparation of Asynchronous Serial Interface
8bitadder
- 串行8位加法器工程,已编译成功.标准代码VHDL语言-Serial 8-bit adder works have been compiled successfully
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源(20位m序列),crc编码(采用串行算法),加噪(用22位m序列产生稀疏的1,然后和编码后的数据异或)。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se