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VHDL学习的好资料--18个VHDL实验源代码
- 20个VHDL实验源代码,包括: 1 交通灯控制器 2 格雷码变换器 3 BCD码加法器 4 四位全加器 5 四人抢答器 6 4位并行乘法器 9 步长可变加减计数器 10 可控脉冲发生器 11 正负脉宽数控信源 12 序列检测器 13 4位流水乘法器 14 出租车计费器 15 多功能数字钟 16 多功能数字秒表 17 频率计 18 七人表决器 19 数码锁 20 VGA彩条发生器
BCD_subtracter
- VHDL编写的7位BCD减法器,可实现带小数点减法运算。-VHDL, 7 BCD subtraction, which can be achieved with a decimal point subtraction.
jianfa_sub
- 基于FPGA的减法器的verilog程序源代码-FPGA-based subtractor verilog source code
jian
- 基于FPGA减法器,实现二进制减法功能,Altera为FPGA初学者详细介绍了FPGA基础知识以及怎样开始进行FPGA设计-FPGA-based subtractor achieve binary subtraction functions, Altera FPGA beginners as described in detail the basics of FPGA FPGA design and how to start
excess-3-code-adder-subtructer
- 余3码excess-3 code加法器和减法器,用vhdl实现-I 3 yards excess-3 code adder and subtractor using vhdl
FinalDesign
- 实现逻辑门电路的绘制以及运算。并且实现了加法器、减法器、乘法器、比较器等运算-Implementation of logic gate drawing and operation. And implement the adder, subtracter, multiplier, comparator and other operations
fdiv
- 用Quarters ii实现对减法器的仿真-In the Quarters ii realize the simulation of the subtracter
test8
- xilinx工程文件,test8.v是源代码,实现了逐位进位的加法器、减法器,和逻辑运算功能。运行通过,仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the simulation is successful.
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
butterfly
- FFT模块里的蝶形运算单元,需要用到加法器,减法器,二选一选择器-FFT module of butterflies, need to use an adder, a subtracter, a second election selector
adder_sub_mul
- 加法器,减法器,乘法器,超前进位,一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.
banjian
- 完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。-Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.
code
- 7位表决器,实现投票选择结果呈现; 减法器编码。-7 bit voting machine, realize the voting choice results present the encoding.
accsub
- 简单的加法器减法器程序代码,Verilog HDL初学者学习可以使用-Simple adder subtractor code, Verilog HDL beginners can use
AnJian_1602
- 计算器设计。采用了现场可编程逻辑器件FPGA设计,并基于VHDL语言实现加减乘除功能,并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形,并下载到试验箱,用实验箱上的按键开关模拟输入,用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能,其结果简单,易于实现。-Calculator design. Using a field programmable logic d
The-display-of-Subtraction
- 利用VHDL语言编写减法器,并利用七段数码管显示。-Using VHDL language to editing subtraction, and the use of seven digital tube display.
Serial-borrow-eight-subtracte
- 本程序实现了串行借位的八位减法器,采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.
vlsi-design2
- 一位8421BCD编码的十进制数加减法器,电路具有进位、借位功能-A 8421BCD encoding decimal adder subtracter circuit has the function, carry out.
加减法器
- 可实现两个4bit补码的加法及减法,有溢出提示(adder with overflow hint)
基于VHDL实现单精度浮点数的加-减法运算
- vhdl 加法器和减法器 希望对VHDL的同学有参考作用(VHDL adder and function as relative reference)