搜索资源列表
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
DividerVHDL
- 使用VHDL进行分频器设计，主要是一些分频的东西，整数分频，小数分频，奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency
xiaoshufenpin
- 基于FPGA的实现小数倍分频代码，广泛应用于数字通信中。-FPGA-based implementation of a small multiple of sub-frequency code, widely used in digital communications.
fenpinVHD
- 任意分频的VHDL 任意分频的VHDL-Any sub-band frequency VHDL any sub-sub-frequency VHDL arbitrary VHDL
DDS-FENPIN
- DDS实现任意小数分频,2.4.6，8和小数分频-DDS to achieve any fractional frequency 2.4.6,8 and fractional-N
experiment6
- VHDL课程实验6，数控分频器的设计。对应不同的输入信号，预置数（初始计数值）设定不同的值，计数器以此预置数为初始状态进行不同模值的计数，当计数器的状态全为1时，计数器输出溢出信号。用计数器的溢出信号作为输出信号或输出信号的控制值，使输出信号的频率受控于输入的预置数-VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set
cysteter
- 分频器，可以求出1--100000000Hz的所有的频率，基于xilinx公司的SPARTAN-3E板子。-Based on SPARTAN-3E of xilinx, using ISE and VHDL, i developed the cysteter.
divide
- 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
onesecond
- 用verilog实现将50M晶振分频，得到1M的功能，本人已经用Quarter9.0运行成功。-To achieve with verilog 50M crystal frequency, get 1M' s functions, I have run successfully with Quarter9.0.
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
N_Separate-frequency-device
- 可以输入0到2的5次方的任意分频的分频器-Separate frequency device
verilog_divdier
- veilog中的常用分频器，包括2分频 4分频 8分频等 开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2
decimal_divison
- 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
PFD50
- 分频器，利用D触发器做的2、3、5分频器-Divider, made use of D flip-flop divider 2,3,5
偶数分频器源代码（可移植）
- FPGA奇偶分频器 可移植 原工程文件 试验没有问题-The FPGA parity divider, portable the original project file
采用STM32制做分频器输出
- 采用STM32制做分频器输出 可以设置分频系数
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
Freq_gen
- XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)
zibiancwt
- morlet小波变换进行分频，里面有详细的注释。(Morlet wavelet transform used to frequency division, which has detailed notes.)