搜索资源列表
fenpin
- 利用vhdl写的分频程序，芯片是LATTICE的(Using VHDL to write frequency division procedures, the chip is LATTICE)
pinlvxianshi
- 通过FPGA中的时钟信号分频作为基准频率，将另一频率作为输入与之比较，并在数码管显示输入频率。(The frequency division of the clock signal in the FPGA is used as the reference frequency, the other frequency is used as input, and the input frequency is displayed in the digital tube.)
FPGA_test_20170620_1
- 对50M的系统时钟进行分频处理，然后控制led的闪灭(Frequency divider controls led.)
fenpin
- 可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。(N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock.)
encoder_clk
- 精确实现奇数分频，将FPGA开发板提供的25MHZ时钟分频为1MHZ，内含测试文件(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)
plusewidth(time_prescaler)
- STM32F103VE芯片，可以实现两个端口测量脉冲的频率以及占空比，为了防止溢出，将其进行了分频处理，可以测量出50Hz左右的脉冲，如果频率过大，则精确度会下降，需要重新更改分频数，程序中不包含输出部分，需要自己添加输出程序，建议直接读取TIM3_CCR2，TIM3_CCR1寄存器的值，然后自己进行转化。程序里面有大概的转换方法，但数值上并不合适，需要进行修改。(STM32F103VE chip, can achieve two port measurement of pulse freque
diver
- 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
plj
- 2秒闸门时间频率计，以及一个分频器，使用FPGA及verilog语言实现(2 second gate time frequency meter)
fenpin51
- 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second fo
EEGfenpin
- 对脑电信号进行波段分频，将脑电信号分为beta、Theta、Alpha、delta四个频段。(Frequency division of EEG signals.)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
oneMHZ
- VHDL语言编写的20Mhz分频器，时间为1秒(20Mhz frequency divider)
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
DIV
- 占空比为50%的七分频电路，实用基于VHDL语言，仿真工具是ISE(Duty cycle of 50% of the seven frequency circuit)
project code5
- 数控分频器的verilog代码在eda上实现(verilog for numerical control divider)
div_3
- 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)
四分频器
- 使用FPGA实现单一频率信号分频为原来的1/4
Lesson07：BJ-EPM240学习板实验1——分频计数实验
- Quartus的分频计数试验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus_frequency division technology test video explanation)
FRECHANGE
- 基于vhdl的分频器程序。可以将50mhz的频率分为1hz(clk divice program base on fpga)