搜索资源列表
fenpinqi
- c语言设计分频器详细资料,里面有大量例程并有相应注解。-c language crossover design details, there are a large number of routines and the corresponding notes.
Odd-number-frequency-division
- 在FPGA中对系统时钟进行奇数分频程序,可适当改变参数对其进行任意奇数分频 verilog HDL语言-Odd number frequency division program based on FPGA
crystal
- 本文以& ∋ ( 型微机远动系统 一!∀ # ∃ ! 为例 , 讨论了微机远动中远 程数据的通讯 问题 。 重点介绍一种新颖实用的频率调制方法一用晶振 分频实现远动) 信号频率调制-In this paper, & ∋ (microcomputer-based remote control system a! ∀ # ∃ !, For example, discusses the remote c
n_evendivider
- 分频器 奇数、偶数分频器,分频数字可以设定-Divider odd, even divider.It divide clock into odd and even frequency.
div_frequency
- 任意分频器,用Verilog HDL实现,只需修改参数可以实现奇数、偶数分频,FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
8bitclk_div
- 任意整数分频计,verilog编写,仿真通过-Any integer frequency meter
fenpin
- 利用单片机的计数器来制作简易分频计,因为P1^0用来模拟外界波形输入,它提供周期为100ms的方波。与T1管脚相连后,T1可对其进行周期计数。 程序中的变量TL1决定着分频系数,其值乘以2即为分频系数。 改变其值可以得到相应的分频输出波形(方波)。 P1^1为输出管脚,将其连接示波器可以看到分频后的波形。-To make use of simple single-chip counter frequency meter, because P1 ^ 0 input waveforms
VHDLdesignexamples
- 半整数分频器、音乐发生器、信号产生器、多功能电子表、交通控制灯、数字频率计的设计实例及习题-Half-integer divider, music generator, signal generator, multi-function digital watch, traffic control lights, digital frequency meter design examples and exercises
31241213verilog_uart_NO
- FPGA串口通讯例程,经我修改绝对可用; 默认48M,9600-8-1/2,如果时钟不同只需修改时钟分频数即可。-The FPGA serial interface communication by the modified routine, absolute can be used The default 48 M, 9600-8-1/2, if the clock different modify it only clock points frequency can.
fp_20m
- 参数化的任意分频,修改参数就可得到任意整数的分频-Parametric any points frequency
digital6counter_top
- 文件描述的是VHDL语言实现的16位计数器,可用于实现时钟的分频或中断控制-Document describes the VHDL language to achieve 16-bit counter can be used to achieve clock frequency or interrupt control
Div5
- 用VHDL编写的奇数分频程序,简单明了,一看就懂。-Written in VHDL odd frequency program, simple and clear, one can understand.
20frequency-divider
- 20分频器的实现,利用Verilog语言-realize 20 frequence device by Verilog
signal
- EP2C5Q208C8 verilog 产生m序列 50M晶振分频得到时钟,可以选择10种时钟- -!-EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
Ex2_PLL_OPT
- quretus ii 的时序优化,在clk输入一定频率的信号,输出端进行分频,得到不同频率信号,从而实现数据采集。
int_div
- 实现任意整数倍的分频功能,已经通过仿真验证无误-Achieve any integer multiple of the frequency function, has been verified by the simulation is correct
fenpinqi
- 200分频的verilog综合仿真源程序,以及仿真波形-200divition-200 points frequency integrated simulation verilog source code, and the simulation waveform-200divition
fenpingjiVHDL
- 基于VHDL语言的分频计,QUARTUS II环境-Based on VHDL frequency meter, QUARTUS II environment
deccount2.5
- 2.5分频器设计,用VHDL编写-2.5 divider design using VHDL
fenpin
- 3分频和1.5分频,可通过此思路进行奇数分频-1.5 and 3 frequency division