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驱动led显示
- //串行驱动led显示, //一个74hc595位移寄存器驱动三极管驱动led位, //两个74hc595驱动led段,方式位5位x8段x2=10个数码管 //5分频,每次扫描时间位1.25ms //定义特殊符号-/ / Serial Driver led, / / a 74hc595 displacement register drives the triode-led drive, / / 2 74hc595 led drive, five-way x8 of x2 = 10 digital
曼彻斯特码
- 今天看了一下从fpga上下的曼彻斯特编解码的程序,感觉不是很清楚,仿真了一下,更迷茫了,大家看看为啥这程序要这么编呢? 程序比较长,不过写的应该还是不错的,看了后应该有收获。 总的思路是这样: 1 通过一个高频的时钟检测wrn信号,如果检测到上升沿,则表明开始编码,将输入的8位数据转为串行,并编码,然后输出。 2 定时信号是从高频时钟16分频后得到的,在wrn上升沿后16分频使能,在编码结束后禁止分频输出。 3 no_bits_sent记录串行输出的位数,应该是从0010到1
8253 8259 time
- 计时程序,对8253进行分频,使用二个计数器,使第二个计数器的OUT作为中断源,送到8259产生中断,在LED上显示时间-time procedures for the 8,253-frequency, the use of two counters, so that a second counter OUT interrupted as a source to have interrupted 8259, the time shown on the LED
remote
- ht47r20遥控程序,红外线载波输出频率这系统时钟的12分频,当系统频率为480KHZ,载波频率为40KHZ-ht47r20 remote control procedures, infrared output carrier frequency system clock frequency of 12 minutes, when the system frequency for 480KHZ, carrier frequency 40KHZ
2分集CDMA跳频通信子程序
- 二分集CDMA跳频通信子程序,计算2分集CDMA跳频通信系统的误码率-two set points CDMA frequency-hopping communications subroutine to calculate two set points Hopping CDMA communication system BER
Q7230
- PLD-N分频程序,使用时可以任意修改(VHDL)-PLD --N procedures can be arbitrary use of Laws (VHDL)
end
- 实现占空比可调的分频时钟输出,一共可以四级可调,也可以自己稍微修改变成任意占空比 。-adjustable duty cycle to achieve the sub-frequency clock output, a total of four adjustable can also be slightly modified into their own arbitrary duty cycle.
32fenpinqi
- 这是用VHDL语言写的32位分频器的程序,可直接运行,看结果,欢迎使用。多指正,交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
clk_divide_3
- VHDL语言编写三分频,可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
freqcntr
- 分频器 几次分频欧次分频 vhdl 语言实现-several hours, frequency dividers Europe subregional frequency VHDL Language
divded-VHDL
- 一个简单的VHDL分频模块,可以嵌套自己的子程序实现任意分频-a simple VHDL-frequency module, which can be nested subroutine achieve their arbitrary frequency -
counter_7seg
- 带分频器的bcd计数电路设计,verilog源码-dividers with the bcd count circuit design, Verilog source
slgtk2
- 在视频显示中用的分频器,可以用来分频点时钟,也可用来控制两个逻辑状态-video display used in the dividers can be used to crossover clock, also can be used to control two logic state
FPGAprogram2
- 半整数分频器电路的VHDL源程序,供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
399
- 用VHDL编写的8位全加器,数字分频器等程序-VHDL prepared by the eight All-Canadian, digital dividers procedures
FMPARTERC
- 采用C语言来编辑分频 测控 计数和储存。和硬件相匹配,用单片机来实现的FM调制器-using C language editing monitoring frequency count and storage. Hardware and matched to achieve MCU FM modulator
8个OFDM-Chirp波形的时频域图及自(互)模糊函数图
- 8个正交OFDM-Chirp分集波形的时域频域图,自模糊函数图和互模糊函数图,文件夹里面有说明文档及参考文献。(Eight orthogonal OFDM-Chirp diverse waveforms, with its time-domain plot and spectrogram, and self-ambiguity functions and cross-ambiguity functions. references are provided.)
三分之一倍频程处理
- 三分之一倍频程程序,信号处理必备,请自用下载(One-third octave program, self-download)
北斗差分定位
- 北斗 0基线 静态单频 单差和双差定位 精度小于1米(OBS single point positioning)
频域的模态参数识别方法
- 频域的模态参数识别方法,包括频域分解法FDD(Frequency domain modal parameter identification methods, including frequency domain decomposition method FDD)