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time_stopwatch
- 通过三个按钮来调节时钟时间，同时通过一个按钮来开启马表功能，马表通过51单片机外部中断0，按钮的信号通过cpld处理过，无抖动，且低电平持续时间极短，只有单片机的一个机器周期。马表功能精确-Three buttons to adjust the clock time while a button to open the stopwatch function, stopwatch by 51 MCU external interrupt 0 button signal processing by
frequency-meter
- 等精度频率测量Mini51B方案,采用51单片机和CPLD实现等精度频率计的设计与现实-Such as the accuracy frequency measurement Mini51B program
Mini51_Os
- 基于51单片机和CPLD实现的示波器，实现数据采集与显示，测量。含有完整的介绍资料和期间选择及原理图。-Based on 51 MCU and CPLD implementation oscilloscope, data acquisition and display, measurement. Containing a complete introduction and during the selection and schematics.
AVR
- java单片机与CPLD综合应用技术电子元器件识别与检测经典入门教程-java integrated application of MCU and CPLD technology electronic components identification and detection of classic introductory tutorial
VGA
- 通过对其编程可输出RGB三基色信号和HS 、VS行场扫描同步信号。当 CPLD接受单片机输出的控制信号后，内部的数据选择器模块根据控制信号选通相应的图像生成模块，输出图像信号，与行场扫描时序信号一起通过15针D型接口电路送入VGA显示器，在VGA显示器上便可以看到对应的彩色图像。-Through its programming output RGB trichromatic signals and synchronization signals HS, VS line field scannin
PWM
- 基于CPLD的多路PWM的实现，单片机串口传送占空比数据-CPLD-based multi-channel PWM to achieve single-chip serial transmission duty cycle data
dianzhen
- 基于CPLD的32*16点阵的设计，单片机通过串口传送数据-32* 16 dot matrix design, the CPLD-based microcontroller through the serial transmission of data
CPLD_AD_AVR
- CPLD程序，程序中实现了PWM波的产生、ADS8364并行高速AD的读写控制，与AVR单片机的通信控制。CPLD以类似外部RAM的方式被AVR读写，AVR单片机只需要向固定的地址写入或者读取即可。 本程序对高速数据采集系统有很好的参考作用，可以以此修改为其他应用场合。-The CPLD program, the program to achieve a PWM wave generation high-speed AD ADS8364 parallel read and write con
shumaguan
- verilog 写的，基于CPLD 的数码管实验，输入端是430单片机，cpld做了38译码器和8位所存-verilog written CPLD-based digital tube experiments, the input is 430 single, cpld made 38 decoder and 8 kept
dog
- C语言，控制cpld的输入端遇上一个代码相配合，实现数码管驱动。使用了430单片机-C language, the control input of cpld encounter a code matched to achieve digital tube driver. Using the 430 SCM
MyFrequencyDesign
- 基于单片机msp430和cpld的高精度频率计。测频范围为0至20MHz。误差在万分之一。可以测量0至100KHz周期，脉宽。-Msp430 microcontroller-based and cpld precision frequency meter. Frequency measurement range of 0 to 20MHz. Error in a million. Can measure 0 to 100KHz cycle, pulse width.
CPLD2AT89C51
- 实现了单片机AT89C51与CPLD之间的双向通信含有可编程逻辑器件发送数据到单片机的VHDL源程序和CPLD接收VHDL源程序-AT89C51 microcontroller and CPLD achieve a two-way communication between the programmable logic device containing a microcontroller to send data to the receiver VHDL source code and CPL
DDS
- 文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和 设计了高分辨率、高稳定度的函数信号发生-Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and Design of high resolution, high stability function
djdfre
- 基于51单片机和cpld的等精度频率计，精度可以达到十万分之一-51 And cpld based on the precision frequency meter, the accuracy can reach one hundred thousandth
MCS51_cpld
- VHDL语言编写的cpld与51单片机总线通信程序。结果应用证明。-VHDL language of the CPLD and 51 microcontroller bus communication program. Application results prove.
GPS
- 本程序实现功能为接受GPS接收机时间信息，并编码形成IRIG-B时间码，同时跟设备总线通过485进行通信。包括原理图，单片机程序及CPLD程序。-This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the
2008082018202568
- 单片机与CPLD串行通信 iic通信 拿来就能用横好-Serial communication with the CPLD iic communications can be used to good use horizontal
freqency_meter
- 等精度原理数字频率计。cpld或fpga文件，和单片机.c文件。-digital frequency meter
phase_shift
- cpld/fpga实现移相功能 d触发器 数据选择器 单片机接口-phase_shift using cpld/fpga
pinlvji
- 频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C-Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digita