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Four-ways-of-contest
- 基于vhdl硬件设计语言而设计的四路抢答器-Based on VHDL designed hardware design language road 4 contest device
altera_fpga
- 用VHDL编写的四路抢答器,附有加减分功能,答题倒计时等。-Written by VHDL four Responder, with addition and subtraction sub function, answer the countdown and so on.
siluqiangdaqi
- 通过VHDL程序设计一个4人参加的智力竞赛抢答计时器,当有某一参赛者首先按下抢答开关时,相应显示灯亮并伴有声响,此时抢答器不再接受其他输入信号。 电路具有回答问题时间控制功能。要求回答问题时间小于等于100s(显示为0~99),时间显示采用倒计时方式。当达到限定时间时,发出声响以示警告。 -VHDL programming by a 4 quiz participants answer in timer, when a participant first press the answe
qiangdaqi
- 基于VHDL与FPGA的四路抢答器的设计与仿真。主要模块:抢答、竞争冒险、抢答倒计时、加分减分、超时蜂鸣、按键消抖、答题记时等模块-VHDL and FPGA-based four-way Responder Design and Simulation. Main modules: Responder, competition and adventure, answer in the countdown, plus minus points, overtime buzzer, key debou
qiangdaqi
- 已VHDL语言实现人抢答器,有抢答计时,答题计时,超时报警功能,通过仿真-VHDL language has been one answer device, there is answer in time, answer time, time-out alarm function, the simulation
jifenqi
- 基于vhdl的智力抢答器的程序设计,功能包括抢答 积分 减分 亮灯 等-Responder based on intelligence vhdl program design features include the answer in points by sub-light, etc.
qiangdaqi
- 一个关于抢答器的HDL设计,完整源代码 Vhdl编程,编译通过-A Responder on the HDL design, complete source code Vhdl programming, compile
qiangdaqi
- 基于quartus II 软件用vhdl语言写的抢答器实验 源代码、最终生成文件全程奉献-Quartus II software-based language used to write vhdl traffic light test source code, the resulting file full dedication
Vies-to-answer-first-8-is
- 这是一个八路抢答器的vhdl程序设计论文,经过eda上机检测通过-This is a vies to answer first the program for 8 VHDL design paper, through computer eda detection through
VHDLkechengsheji
- 这是VHDL的课程设计 包含三个题目 流水灯 两人抢答器 四人抢答器 刚做完 传上来 共享-This is a curriculum design VHDL contains three topics water lights answer two answer four just finished Chuan-up share
MultQD
- 基于FPGA的VHDL实现的多人抢答器,可供课程设计参考!-FPGA-based VHDL people Responder available for curriculum design reference!
qiangdaqi
- 基于可编程软件的抢答器设计,使用的是VHDL语言进行编程-Based on programmable software Responder design,Use VHDL language to program
Responder
- 基于VHDL语言的抢答器,各个模块的功能1.抢答器同时供N名选手,(此处假设4个)分别用4个按钮S0~ S3表示。 2.设置一个系统“开始复位”开关S,该开关由主持人控制(当主持人按下该开关后以前的状态复位并且开始计时抢答)。 3.抢答器具有锁存与显示功能。即选手按动按钮,锁存相应的编号,并在LED数码管上显示,同时扬声器发出报警声响提示。选手抢答实行优先锁存,优先抢答选手的编号一直保持到主持人将系统清除为止。 4. 抢答器具有定时抢答功能,且一次抢答的时间(0-99S)。当主持人启
qiangdaqi11
- 用VHDL语言设计一个抢答器系统,能反映抢答者的抢答并作出回应,xilinx平台-design a answer competition system with language VHDL and platform Xilinx
qhqjh
- vhdl 设计得四位抢答器,有图和源码及设计思想-VHDL designed to four vies to answer first device, a figure and the source code and design thought
Four-intelligent-responder-
- 四路智能抢答器的VHDL实现,具有开始和复位功能,同时具有答题倒计时功能-Four intelligent responder VHDL implementation, with start and reset function, simultaneously has the answer countdown function
Control
- vhdl, 抢答器的一些功能,主持人可以控制4个按键,很好的课程设计-VHDL, some of the features of Responder, the host can control the four buttons, good course design
VHDLqiangdaqi
- 基于Quartus的抢答器的设计,用VHDL硬件电路设计实现的模拟电路,用FPGA开发板可看到效果,一共八个按钮,有复位键-Quartus Responder based design using VHDL hardware circuit design and implementation of analog circuits, FPGA development board can see the results, a total of eight buttons, with reset bu
myqdq
- 该项目实现了一个四路的智力抢答器的基本功能,像抢答鉴别,计时,计分等。-A responder that is realized in VHDL
qdq
- 用VHDL语言实现四路抢答器功能,抢答之后不能再抢答,除非主持人按下复位键。可以显示四个选手分数,显示答题倒计时的时间,主持人可以控制加减分,分数通过显示屏显示。使用软件Quartus Ⅱ,可以将程序导入FPGA并能运行。有竞争模块,显示模块,分频模块,加减控制模块,计数器模块,蜂鸣器模块,译码模块,计分器模块,锁定模块等。-VHDL language with four Responder function can not answer after answer, unless the hos