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- 基于CPLD的VHDL语言数字钟(含秒表)设计及程序 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。-The VHDL language based on CPLD digital clock (including a stopwatch) design and program By usin
soc-count
- soc 的 vhdl语言设计的基于嵌入式 数字钟-soc vhdl language design based on embedded digital clock
clock
- VHDL编程数字钟，能够实现时间校正，闹钟，整点报时，显示日期，倒计时等功能。-The VHDL programming digital clock, time correction, alarm, hourly chime, such as date, countdown function.
Digital-clock-design
- 用VHDL语言设计数字钟.实现以下功能：正常走表，时间设置，闹钟设置，整点报时，闹钟提醒。-Digital clock using VHDL language . Achieve the following functions: normal walking table, time settings, alarm settings, the whole point timekeeping, alarm.
cnt60
- vhdl数字钟，有校时校分整点报时的基本功能-vhdl digital clock school, the school divided the whole point timekeeping function
ep1c12_15_clock
- 数字钟设计：该程序完成了在Quartus Ⅱ上使用VHDL语言实现的24小时数字钟设计-Digital clock design: the process is complete Quartus Ⅱ a digital clock using VHDL language design
zhangxing
- 利用vhdl语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s-Digital alarm clock, clock and alarm functions
CPLD-digital-clock-design
- 基于CPLD实验板的多功能数字钟设计，运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
bcd
- 十进制转换为BCD码，可以用于数字钟的设计，及其涉及到LED显示的程序中去，是VHDL的-Converted to decimal BCD code, can be used in the design of the digital clock, LED display program involves VHDL
duogongnengshuzizhong
- 基于Max+plus2软件的Verilog VHDL语言的数码管显示多功能数字钟-Multifunctional digital clock digital tube based on Max+plus2 software Verilog VHDL language
digital-colok
- 用quartusII编写的vhdl代码，在板子上输出的显示就是数字钟，也可以重置、设置时间。-With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.
num_clk
- 基于FPGA的数字钟程序 VHDL语言编写-failed to translate
miaobiao
- 用VHDL编写的一个数字钟，可以完成计时功能。-VHDL prepared a digital clock, you can complete the timing function.
Multi-function-digital-clock
- 1、 了解数字钟的工作原理。 2、 进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、 掌握VHDL编写中的一些小技巧。 -1, to understand digital clock works. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
multiclock
- 以VHDL为基础的多功能数字钟的实现功能程序，包括时钟，闹钟，计数等功能。-In VHDL-based implementation of multi-function digital clock procedures, including clock, alarm clock, counting and other functions.
FPGA
- 数字钟，实验程序描述，vhdl语言描述，看电视剧广发卡三季度发卡了-Digital clock, experimental procedures described, vhdl language descr iption, watching TV wide hairpin hairpin three quarters of the
clock
- 用VHDL编写的数字钟，可以走时，读秒，用作闹铃，整点报时-Using VHDL digital clock, you can take time, countdown, for alarm, hourly chime, etc.
alarm
- VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa