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sine_wave_2011_0329
- 正弦波波形发生器,verilog编写,Modsim仿真。-sine wave genonter
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手,本文给出了DDS的详细设计过程,包括各个模块的设计思想,电路图,Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值,最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
signal_generator
- 信号发生器 可以通过该程序产生对应的波形 用Verilog语言编写实现 希望能对大家有帮助-The signal generator can generate through the program corresponding to the waveform using the Verilog language
LSY_wave
- 比赛时写的李萨如波形发生器的代码,用verilog写的,里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
zhengxian
- verilog的正弦函数信号发生器的设计。可生成不同的正弦函数信号波形。-verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
10010sequece-detector
- 序列发生器,Verilog HDL语言描述,包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
M=15generator
- 模15序列发生器,Verilog HDL语言描述,包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
zhengxianbo
- 正弦波发生器,基于verilog语言编写的,不用用DAC模块,直接输出0和1电频,经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
DDS
- 基于fpga的正余弦波形发生器,Verilog代码,测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
six_wave
- 产生六种波形的DDS信号发生器,用verilog实现,有modersim仿真程序和结果,产生正玄波,方波,锯齿波,三角波,阶梯波。实现完全可用-the dds can output six signal,write in verilog。
wave_gen
- 波形发生器,可以产生正弦波,锯齿波,方波。Verilog语言编写-Waveform generator, can generate sine wave, sawtooth wave, square wave. Verilog language
DDS_FPGA
- 任意波形发生器FPGA实现,Verilog语言编程,试验板为DE0-Arbitrary Waveform Generator FPGA implementation, Verilog language programming, test panels of DE0
dac_900
- DAC900芯片驱动的Verilog语言描述,亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用,也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
dds_generater
- 波形发生器,可以生成正弦波、三角波、方波、锯齿波;可以选择输出频率和幅度,基于DDS设计,verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
verilog-sin
- FPGA开发sin波形,用verilog写的正弦波发生器。-FPGA development sin wave with verilog write sine wave generator