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jisuanjizucheng3
- 计算机组成原理课程设计。基本模型机的设计—跳转、转移指令的实现 熟悉微程序控制的原理，掌握微程序的编制、写入并观察运行状态。明白每一条指令在内存、CPU中的存取和执行流程-Principles of curriculum design computer components. The basic model design- Jump, the realization of the transfer of command are familiar with the principle of mic
VHDLdanpianji
- 本文首先对MCS8051单片机的原理进行介绍和分析；接着介绍使用EDA技术，用VHDL语言完成了8051单片机的设计工作；MCS8051单片机的CPU和数模转换器的设计运用了算术逻辑单元ALU算术运算的算法实现和控制单元的状态机；以及数模转换器的∑-△调制方法的实现。通过如上的算法实现，可以看出VHDL语言在算法级的设计上具有很多的优势和特点。使用EDA技术设计的结果既可以用FPGA／CPLD来实施验证，也可以直接做成专用集成电路(ASIC)。-VHDL
UART
- 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
zhuangtaiji
- 有限状态机及其设计技术是实用数字系统设计中的重要组成部分,也是实现高效可靠逻辑控制的重要途径,本程序为单进程moore型有限状态机底层设计源代码.-This procedure as a single process moore-type finite state machine underlying the design of the source code.
VHDLprogram
- 含有各类寄存器，AD和DA转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
Finit_state_machine_in_C
- C实现一个状态机,我做毕业设计，实现自组织网络，三个节点-Finit state machine implemented in C code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
trafficcontrol
- 基于有限状态机的VHDL交通灯程序， 其中包括两种不同的思路；设计两种控制器 读者还可以根据实际应用更改设计，十分方便。-jtd vhdl traffic time control and led display
user-interface
- User Interface的设计,包括显示DAQ,Movie,Flash,Website.状态机的设计-the code of User Interface
8bit_LED_scan
- 8位七段码动态扫描控制VHDL设计。动态扫描模块，延时模块，译码模块。设计采用状态机思路。-The design of scan display of 8bit-segment-LCD based on VHDL
EDA
- EDA实验讲义GK 包含GW48 EDA系统使用说明以及许多实例。比如有时钟使能的两位十进制计数器原理图输入设计、用状态机对ADC0809的采样控制电路实现、硬件电子琴电路设计-EDA experimental GK notes GW48 EDA system contains, as well as many examples of use. For example, there are two clock-enabled input decimal counter schematic des
SDRAMVerilogHDL
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
15AlteraIP
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
sequence_check
- 用状态机实现序列检测器的设计，并采用ROM结构输入待测序列进行仿真测试。-sequence inspector
1
- VHDL语言在电路设计中的优化 vhdl语言，毛刺，状态机-VHDL language in the optimization of circuit design in vhdl language, burr, state machine
FSM_Mealy
- 借助该MEAL状态机源码您就可以轻松设计自己需要的状态机-MEAL state machine with the source code you can easily design their own state machine needs
EfficientSynthesizableFiniteStateMachineDesignusin
- 高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
labviewbiaozhunzhuangtaiji
- labview 标准状态机,介绍基于labview的状态机的设计,设计一个很好的例子.-labview standard state machine, introduced labview-based state machine design, design a good example.
testgray
- 有限状态机FSM编程设计及测试，代码合一了，以三位gray码为例，在modulesim5.7上测试通过。-Finite state machine FSM programming design and test, code-one, and with three gray code, for example, in the modulesim5.7 on the test.
miaobiao
- 用VERILOG实现秒表的开发设计，(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理；(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发；(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c