搜索资源列表
AD574
- AD574控制器的VHDL程序，用状态机设计的AD574器件的控制器FPGA硬件设计，可以代替单片机的功能-AD574 controller VHDL program, the state machine design AD574 device controller FPGA hardware design, can replace the function of the microcontroller
6_VHDL-application-design
- VDHL应用实例，包括组合逻辑电路设计，时序逻辑电路设计，存储器设计，状态机设计 -VDHL application design samples, including combined logic design, timing logic design, memory design, and status machine design
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
fsm
- rfid 电子标签设计数字基带处理状态机设计-rfid electronic card digital signal processing of fsm
MYCRC
- 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但
FSM_Mealy
- Mealy型有限状态机设计，设计软件quartus，有详细注释-Mealy type finite state machine design, design software, quartus, with detailed notes
FSM_Moore
- Moore型有限状态机设计，设计软件quartus，有详细注释-Moore-type finite state machine design, design software, quartus, with detailed notes
Program
- 用VHDL状态机设计一个8位序列信号检测器。-Design a state machine in VHDL 8-bit serial signal detector.
communication-controller
- 该异步通信控制器主要采用状态机设计完成。包括异步发送端和异步接收端。可异步进行信号的收发-The asynchronous communication controller mainly USES the state machine design completed. Including asynchronous the sender and receiver asynchronous. Can signal to send and receive the asynchronous
schk
- 用状态机实现序列检测器的设计，熟悉用状态机设计各种序列检测器的思路和方法-Sequence detector state machine design, familiar with the ideas and methods of the various sequence detector state machine design
state
- verilog 应用状态机设计的序列检测器-verilog ，state machine
State-machine-
- FPGA设计资料,新手入门资料，，状态机设计，-FPGA design
schk
- 熟悉用状态机设计各种序列检测器的思路和方用状态机实现序列检测器的设计-Familiar with the various sequence detector state machine design thinking and to use the state machine to achieve the design of the sequence detector
how-to-write-state-machine
- FPGA状态机设计中的问题，怎样写好三段式状态机，对于FPGA设计者很好的资料-FPGA state machine design issues, how to write a three-state machine, very good information for FPGA designers
vhdl
- vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。-vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.
state-machine-program
- Verilog三段式状态机.pdf Verilog时序电路及状态机设计.ppt Verilog有限状态机设计.ppt 状态机.ppt 用状态机原理进行软件设计.pdf 有限状态机.pdf 有限状态机.ppt 状态机原理及用法.pdf 对状态机初学者有帮助。 -Verilog three-state machine the pdf Verilog Sequential Circuits and the state machine design. Ppt Veri
Automatic-beverage-vending-machine
- 自动售饮料机，只可投入5毛和1块钱，每瓶饮料为2.5元，要求应用状态机设计该系统，并编写Testbench。 输入信号定义： clk：时钟输入 ngreset：复位信号 half_yuan：五毛钱 one_yuan：一元钱 输出信号定义： dispense：表示机器售出一瓶饮料 collect：用于提示投币者取走饮料 half_out：表示找回五毛钱-Drinks vending machine can only be put into hair
traffic_led
- 基于FPGA芯片设计多功能交通灯，该模块利用状态机设计，能实现交通指示功能-FPGA-based chip design multi-functional traffic lights, the module state machine design, traffic directions
EDA
- EDA交通灯程序.学习利用计数器和状态机设计十字路口交通灯控制器。设计一个简单十字路口交通灯控制器。该控制器控制甲乙两道的红、黄、绿三色灯，指挥交通和行人安全通行。-EDA traffic lights program. Learning to take advantage of the counter and state machine design crossroads traffic light controller. Design a simple crossroads traffic
VHDL
- 基于VHDL语言的交通灯设计:通过状态机设计实现交通灯的红黄绿三种灯显示.其功能包括:红绿黄灯显示,倒计时功能,测试功能,手动控制功能.-Based on VHDL design of traffic lights: red, yellow, and green traffic lights, three lights through the state machine design features include: red, green, yellow, countdown function