搜索资源列表
Sequence-Detector-State-Machine
- 状态机序列检测器设计，包含程序在内，该程序是检测1101-Sequence detection state machine design, including the program included, the program is to test 1101
digital-clock
- 数字钟是计时仪器，它的功能大家都很熟悉。本实验对设计的电子钟要求为： 1．能够对s(秒)、min(分)和h(小时)进行计时，每日按24h计时制； 2．min和h位能够调整； 3．设计要求使用自顶向下的设计方法。 数字钟的功能实际上是对s信号计数。实验板上可提供2Hz的时钟，二分频后可产生s时钟。数字钟结构上可分为两个部分c计数器和显示器。计数器又可分为s计数器、min计数器和h计数器。s计数器和min计数器由6进制和10进制计数器构成，小时计数器较复杂，需要设计一个24(或12)
JohnFSM
- java 实现的状态机，给出一个初始状态，通过一定条件，得到一个终止状态-java implementation of the state machine, given an initial state, by certain conditions, to get a termination state
Road_Test
- 采用状态机实现的装考的C语言程序源码，非常全面，经验证，效果不错，欢迎评论-Installed using the state machine implementation of the C language test program source code, very comprehensive, proven, well, welcome to comment
you-xian-zhuangtaiji
- 状态机在桩考系统中的应用，如何使用状态机等，以及桩考的流程，也是挺不错的资料哈-State machine in the Zhuangkao system, how to use the state machine, as well as Zhuangkao process, the information is very good Kazakhstan
moor
- 用fpga 实现状态机的设计 学会设计状态机是 用fpga的基本功-Fpga implementation with the design of state machine design state machine is learn the basics fpga
ADC0804-Driver
- FPGA 本实验是用 驱动 adc0804 这个芯片，由于驱动这个芯片要使用有一定的时序控制，所以本实验用状态机来控制-The experiment is driven FPGA adc0804 this chip, the chip to be used as drivers have a certain timing control, so the state machine to control the experiment
kongtiaokongzhi
- 用状态机方式编写的简单的空调控制器，根据外界不同的温度控制制冷升温-With the state machine approach to the preparation of a simple air-conditioning controller, according to outside temperature of different refrigerant temperature control
fangdoudonganjian
- 本程序的开发环境是VHDL语言环境。本程序采用双进程即双process的方式，实现按键防止抖动编码电路的功能。具体是采用行和列双向选中控制的方式，来判断哪个按键被按下。本程序共有三个状态。 本程序是VHDL课程的状态机的典型应用实例！-This procedure is the VHDL language development environment environment. The program uses two-way process that double process to a
FA
- 有穷自动状态机的实现，以及实现各个状态的遍历，并将显示所有可能的路径。-Automatic finite state machine implementation, and traverse the states to achieve, and will display all possible paths.
ADC0809-
- ADC0809 采样控制电路设计报告 状态机实现方式-ADC0809 sampling control circuit design report state machine implementations
State-machine
- 实现了一个简单状态机的转换功能，用Verilog语言。-State machine implements a simple conversion function, with the Verilog language.
code
- 一个51上简单操作系统的实现,基于状态机原理，实现休眠、消息等机制-51 operating system on a simple realization of the principle based on state machine to achieve sleep, news and other mechanisms
text
- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号。本系统用状态机来实现序列（1110010）的序列检测器的设计，若系统检测到串行序列 1110010 则输出为 1 ,否则输出为 0 ，并对其进行波形和功能仿真。-Sequence detection can be used to detect one or more groups formed by the binary code pulse train signal. The system implemented by the st
VHDL
- VHDL程序(含任意波发生器，一些芯片的驱动，以及状态机的典型设计等)-VHDL program (including arbitrary waveform generator, a number of driver chips, and a typical state machine design, etc.)
LCD1602
- LCD1602在DE2-70显示,是利用状态机来实现-LCD1602 display in the DE2-70, is the use of state machine
sign
- FPGA实现序列发生器，用MEALY状态机实现-failed to translate
vhdl-xiyiji
- 基于quartus2的vhdl状态机——洗衣机编程应用，采用EDA自顶向下的设计方法。-The vhdl state machine based quartus2- washing machine programming applications, the EDA top-down design approach.
vhdl
- 8421BCD码同步计数器,序列信号发生器,状态机设计-8421BCD code synchronization counter, serial signal generator, the state machine design
2
- 使用变量的状态机 library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT(clock,x : IN BIT z : OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0,s1,