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IEEE-standard-Verilog-HDL
- IEEE 标准 Verilog 硬件描述语言，这是IEEE 制订的verilog 标准参考文档-IEEE Standard for Verilog Hardware Descr iption Language
Asynchronous-FIFO-Design
- 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
verilog-hdl
- verilog hdl quartues-硬件描述语言， 数字系统设计，设计数字系统，灵活方便，更改方便，设计流程时间段
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
1024point-fft--using-verilog-hdl
- 1024点快速傅里叶变换，使用verilog hdl硬件描述语言-1024point FFT，using verilog hdl
LAB-2
- 用FPGA实现对VGA的控制，没有用到niosII,只是用硬件描述语言verilog。整个工程。-With FPGA VGA control is not used niosII, just verilog hardware descr iption language. The entire project.
My-szz-Verilog
- 用硬件描述语言编写的电子钟程序，并可以在试验箱上面实现的-Electronic clock program using a hardware descr iption language, and can be achieved in the chamber above the
verilog
- jpeg源码，图像编码的硬件描述语言设计,可用作硬件加速处理参考-jpeg source, image coding hardware descr iption language design
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
pay-verilog
- 出租车计价器程序代码，硬件描述语言，VHDL—verilog-chuzuche meter，VHDL—verilog
QuartusII
- 此模块为altera官网提供模块，使用硬件描述语言Verilog语言编写的FFT基于FPGA实现。-This module provides a module for the Altera website, the use of hardware descr iption language Verilog language FFT based on FPGA.
yinjianmiaoshuyuyanVerilog(disiban)
- 这是硬件描述语言verilog的第四版，希望对大家的学习有帮助。-This is a hardware descr iption language Verilog fourth edition, I hope to learn from everyone.
verilog-book
- 非常适合初学者的一本入门级的verilog硬件描述语言参考书。-Very suitable for beginners an entry-level verilog hardware descr iption language reference books.
verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台，结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
axi_ad9361_tx_channel
- 采用硬件描述语言verilog进行AD9361芯片实现的代码-AD9361 using hardware descr iption languages Verilog code that chip
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
hardware-qpskmodulate1
- 采用硬件描述语言verilog进行QPSK变换的实现的代码- Using hardware descr iption languages Verilog implementation of QPSK converter code
hardware-rake_mrc1
- 采用硬件描述语言verilog进行RAKE MRC变换的实现的代码-Using hardware descr iption languages Verilog implementation ofRAKE MRC converter code
lcd_driver
- LCD驱动，硬件描述语言Verilog编写,色深16位，分辨率为800*480-LCD driver Verilog hardware descr iption language written in 16-bit color depth, resolution of 800* 480
TX
- 串口发送控制程序！在一帧的发送下，经过串口协议编写的硬件描述语言verilog！-Serial transmission control program!