搜索资源列表
rlut
- ldpc译码器的部分校验和的原理图转化为VHDL语言。-ldpc decoder part of the checksum of the schematic diagram into VHDL language.
2-Decimal-BCD-Decoder
- 二-十进制BCD译码器,就是用VDHL编写的将二进制转化为十进制的BCD译码器-2- Decimal BCD Decoder, is to use VDHL written into the binary decimal BCD decoder
VHDL
- 1.7段数码译码器 2.4人表决器 3.8421码十进制计数器 4.9秒减计数器-1.7 Section 2.4 digital decoder person voting 3.8421 yards in 4.9 seconds by a decimal counter counter
VHDLqiangdaqi
- VHDL四路抢答器该任务分成七个模块进行设计,分别为:抢答器鉴别模块、抢答器计时模块、抢答器记分模块、分频模块、译码模块、数选模块、报警模块,最后是撰写顶层文件。-VHDL four Responder divided into seven modules of the design task, namely: Responder identification module, timing module Responder, Responder scoring module, frequency
decoder
- 38译码器VHDL语言 可以实现38译码器的功能-38 decoder VHDL language
VHDL
- 译码器。半加器,全加器。。。包括源程序和仿真波形-Decoder. Half adder, full adder. . . Including the source and the simulation waveform
VHDL
- 电子设计自动化软件下的3-8位译码器,触发器的VHDL 代码-Electronic design automation software under the 3-8 bit decoder, triggers the VHDL code
RS
- RS译码器的设计,使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
74-Hamming-code-encoder-and-decoder
- 基于VHDL实现(7,4)汉明码的编码器和译码器-VHDL-based implementation (7,4) Hamming code encoder and decoder
VHDL
- EDA技术以EDA软件工具为开发环境,以可编程逻辑器件为实验载体,实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件,本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表,译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计,然后进行编程、时序仿
VHDL
- 基本的VHDL程序代码,如加法器,乘法器,译码器,编码器等等,希望能给大家一些帮助,分享万岁!-Basic VHDL code, such as adders, multipliers, decoders, encoders, etc., I hope to give you some help, to share long live!
rom_decoder_ram
- 三八译码器 VHDL语言 ROM RAM-Thirty-eight decoder
ps_decoder3_12_80_mod
- PS-LDPC码译码器的Verilog程序-PS-LDPC code decoder of the Verilog program
VHDL
- 3-8译码器 与程序 164译码器 时钟编程的VHDL程序-3 to 8 decoder and program 164 decoder clock of VHDL program. Programming
ug_rs-compiler
- altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
7shumaguanEDAfangzhen
- 用VHDL语言的七段数码显示译码器设计 已仿真出结果 用来学习7段数码显示译码器设计;学习VHDL的CASE语句应用及多层次设计方法。-VHDL language of seven-segment display decoder has been designed simulation results were used to study a 7-segment display decoder design learn VHDL CASE statement applications and
vhdl
- VHDL实验 7段数码管译码器设计与实现-VHDL experiments 7-segment LED decoder design and implementation
dc3and8
- 3-8译码器VHDL工程源代码,含工程、VHDL源码、下载文件等-3-8 decoder VHDL project sourcecode
vhdl
- 利用一个简单的三八译码器来讲述VHDL设计, 熟悉VHDL开发环境-this is a example that is used to introduce the VHDL lauguage ,and you will be asmiliar the envrionment
VHDL
- 加法器、寄存器、半加器、译码器的硬件描述语言的描述-describe summator ,register,half adder,decoder with VHDL