搜索资源列表
7-segment_digital_tube_decoder_design
- VHDL中7段数码管译码器设计与实现的实验报告，包括源代码-VHDL in the 7-segment digital tube decoder design and implementation of the experimental report, including the source code
decoder38
- vhdl编写的38译码器 完全文件，打开可用-vhdl decoder written 38 full document, open the can
vhdl
- 3分频 器，LED分位译码电路，交通控制器，序列检测器-four programs based on vhdl
VHDLseven-segmentdecoder
- VHDL在液晶显示上的七段译码器源码,应用于FPGA,ASIC等硬件设计-VHDL in the seven-segment liquid crystal display on the decoder source code, used in FPGA, ASIC and other hardware design
2
- BCD码七段译码器CC4511,用VHDL语言来描述CC4511。-BCD code seven-segment decoder CC4511, using VHDL language to describe the CC4511.
decoder38
- 基于vhdl的38译码器的实现，很实用的示例程序，物理可实现-decoder 38 based on quartusII
3_8_DISPLAY
- vhdl实现3－8译码器，并通过7段数码管显示程序-vhdl decoder to achieve 3-8, and by 7 segment LED display program
yimaqi
- 译码器，硬件描述语言VHDL。。代码简洁，功能实现的好。-Decoder, VHDL language
coder1
- 这是一用VHDL语言描述的8线-3线译码器,希望对大家有用-This is a descr iption using VHDL, 8-line-3 line decoder, we want to be useful
decoder
- 这是一用VHDL语言描述的3线-8线译码器,希望对大家有用-This is a descr iption using VHDL, 3-wire-8 line decoder, we want to be useful
07401200310
- VHDL原程序包括译码器，半加器，全加器-VHDL program, including the original decoder, the half adder, full adder
YMQ
- 7段译码器、实现数码管从0到F的显示的VHDL程序-7 segment decoder
shiyan3
- 利用文本编辑器和VHDL语言设计一个半加器和或门，将其定义成Symbol图元，在图形编辑器中利用这些Symbol将其设计成一个全加器。下载到CPLD芯片中，接入输入电平信号和输出LED显示器。还有一个4-16译码器的VHDl程序-adder 4-16
1
- vhdl 建立3-8译码器，这里面是步骤和代码-3-8 decoder vhdl established, and there are steps and code
4-16.doc
- 4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中-4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device
jiyuxianxfzmdymqyj
- 基于VHDL的线性分组码编译码器设计-jiyuVHDLdexianxinfzm
decoder_38_vhdl
- FPGA的三八译码器的实现，VHDL编写-FPGA implementation of the March Eighth decoder, VHDL writing
decoder4_16
- 在文本编辑器下有vhdl语言编写416译码器-In a text editor written in 416 under the decoder vhdl
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
HDB3ymq
- 通信原理课程设计 关于HDB3译码器的VHDL语言实现-use vhdl to transform HDB3