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ise6.3ad0809_test
- 本程序为VHDL语言编写的ADC0809的采样程序 并用DA0800恢复-procedures for the preparation of the VHDL ADC0809 the sampling procedures used to restore DA0800
subr
- VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数,然后在Load线上送高电平,把数据存到除法计算电路内部,然后经过若干个时钟周期,计算出商和余数,并在C和D端输出。 其实现方法是,将除法器分为两个状态:等待状态与运算状态。 开始时除法器处于等待状态,在该状态,在每一时钟上升沿,采样Load信号线,若是低电平,则仍处于等待状态,如果采样到高电平,除法器读取A,B数据线上的输入数据,保存到内部寄存器a_r,b_r,置c_r为0,d_r为a_r,判断除数是否为零,若
8bitsine
- 8bit采样sine波形发生器,一共两个文件,各自用VHDL和VERILOG编写,通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
mif
- 使用metlab生产正弦波和三角波的采样值,供vhdl等语言调用来产生波形-use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms
VHDLsourcecode
- VHDL编写的基于过采样的串口代码,在epm3256中编译通过,值得参考。-Written in VHDL-based over-sampling of the serial code, compiled by the epm3256, worth considering.
adc0809
- 基于ADC0809的采样控制电路的实现,虽然简单,但是代码写得规范,值得学习-ADC0809 based sampling control circuit implementation is simple, but the code is written specifications, it is worth learning
rs232
- 用vhdl实现fpga串口通信 包含 波特率生成 发送模块 接收模块 过采样 signaltap使用-Vhdl fpga serial communication with the realization of sending module contains the baud rate generation receiver module using oversampling signaltap
MATLAB
- 基于 MATLAB 的语音信号分析与处理的课程设计.录制一段自己的语音信号,并对录制的信号进行采样;画出采样后语音信号的时域波形和频谱图;给定滤波器的性能指标,采用窗函数法或双线性变换设计滤波器,并画出滤波器的频率响应;然后用自己设计的滤波器对采集的语音信号进行滤波,画出滤波后信号的时域波形和频谱,并对滤波前后的信号进行对比,分析信号的变化;回放语音信号-MATLAB-based voice signal analysis and processing of the curriculum. Re
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中,采用FPGA实现快速的FFT运算,采用数字锁相环来同步被测信号,以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现,该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
FPGAADC(VHDL)
- 用FPGA实现的ADC采样器(用VHDL编写)-ADC with FPGA-sampler (using VHDL written)
AD
- 利用VHDL是实现对ADC0809对信号是实现采样-VHDL is used to realize the ADC0809 samples the signal is achieved
msk_mod
- msk 调制解调源码,每符号采样8次。对pn码进行调制后,进行解调,解调过程含:符号差分,中值滤波等过程。-msk modem source code, sample 8 times per symbol. Modulation of the pn code after the demodulation, the demodulation process including: symbol differential, the value of the filtering process.
shishi
- 基于FPGA的实时采样系统设计!双口ram典型应用!-FPGA-based real-time sampling system!
pid
- 采样量化,实现数字PID功能,并观察了PID实现后的误差。包含测试文件和实验报告-Sample quantization, digital PID function, and after observing the realization of the error of PID. Contains the test documents and test reports
adc0809
- 利用FPGA控制ADC0809采样电压,并通过数码管显示电压数值-ADC0809 FPGA control by sampling the voltage and the voltage value through the digital display
AD7888-sampling-with-VHDL
- 用VHDL语言编写的AD7888模数转换芯片的采样程序- AD7888 sampling with VHDL program
AD0809
- AD0809的采样控制设计,经过试验成功了得-AD0809 sampling control design
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计,如FIR、IIR滤波器,CORDIC算法,多重采样率信号处理,FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters,VHDL/Verilog code
实验21 DAC实验 - 副本
- 实现采样DAC功能,采用VHDL语言,附有源代码和整个工程。(Implement the sampling DAC function)
AD7895
- 读取AD7895 的12位ADC转换值,连续读取方式,采样速率为20mS 一次。(Read the 12 bit ADC conversion value of AD7895.)