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AES加密的VHDL源码
- 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
AES加密算法的VHDL实现
- AES加密算法的VHDL实现
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
cunzip
- AES CODE FOR DECRYPTION
Rijndael
- AES USING PICOBLAZE CODE
aes_core_latest-1.tar
- Simple AES (Rijndael) balance implementation and trade off size and performance-Simple AES (Rijndael) balance implementation and trade off size and performance
aes
- 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
top_module
- AES Encryption Algorithm.... This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module-AES Encryption Algorithm.... This Module gives the basic overview to
sbox
- verilog code for s-box generation for AES algorith
aes_pipe_latest.tar
- implementation of AES encryption algorithm in vhdl/verilog
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
avs_aes_latest.tar
- AES algorithm decryption Encryption
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
AESvhdl
- AES vhdl, encryption, decryption code
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
aes-project-master
- aes project vhdl FPGA