搜索资源列表
COUNT_ASYNC_4SUB
- 4位异步二进制减法计数器,利用QUARTUS II 9的CPLD/FPGA-4bit_count_asyn_sub
timing
- 对输入CPLD/FPGA特定口的前后两个脉冲间隔进行计数并输出-timing for the break of 2 impulses into the certain input of CPLD/FPGA and output
fifo_vhdl
- 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
CPLD
- verilog编写的加减6路可逆计数器,用于FPGA对6路脉冲信号的计数-verilog written addition and subtraction 6 way reversible counter for FPGA on the 6-channel pulse count
logiclock_makefile
- 一个CPLD/FPGA的程序,初学者可以看看,应该有帮助的-Code for CPLD/FPGA,useful !
Electronics---Digital---Cpld-And-Fpga---Fpgasigne
- Fpga Cpld Quick Start Guide with "Altium Designer"
ADc
- 与单片机相比,用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809,根据ADC0809的工作时序使用CPLD产生该控制信号,CPLD启动AD转换后,得到的数据送至单片机并在PC机及数码管上显示AD转换结果。-Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of
Based-VHDL-Fpga-Development
- 基于Altera FPGA/CPLD的电子系统设计及工程实践书籍源代码-Book source code of Altera FPGA/CPLD-based electronic system design and engineering practice
FPGA
- FPGA开发全攻略_工程师创新设计宝典.FPGA 是英文 Field Programmable Gate Array 的缩写,即现场可编程门阵列,它是在 PAL、GAL、CPLD 等可编程器件的基础上进一步发展的产物。它是作为专用集成电路(ASIC)领域中的一种半定制电路而出现的, 既解决了定制电路的不足,又克服了原有可编程器件门电路数有限的缺点。它是当今数字系统设计的主要硬件 平台,其主要特点就是完全由用户通过软件进行配置和编程,从而完成某种特定的功能,且可以反复擦写。在 修改
inx-ISE-9.x-fpga
- inx ISE 9.x fpga&cpld设计指南 光盘附带内容,很好的工程实例-Design Guide CD-ROM included with the content, good engineering examples
FPGACPLD
- 描述FPGA与CPLD的区别,用于为初学者提供fpga与cpld的认识学习-Describe the difference between FPGA and CPLD, fpga and cpld understanding of learning for beginners
verilog-example
- verilog实例,是开发cpld、fpga时参考程序,很实用-Verilog example, is the development of CPLD, FPGA reference procedures, it is practical
the-experience-of-fpga
- 很好的学习资料,主要讲解了一些FPGA/CPLD的设计经验,比较适合初学者进行学习。-A very good learning materials, mainly on the FPGA/CPLD design experience, more suitable for beginners to learn.
fpga-cpld-tool-make
- fpga调试工具制作 具有较好的实用价值-the fpga debugging tools to create good practical value
maxv_5m570z_SCH_PCB_PA
- Altera公司的Max 5 GX系列的原理图和pcb文件,注意,是capture及pdf格式的原理图和allegro格式的PCB文件,稍微修改修改就可以用在您的设计中,让fpga的硬件设计变得简单和高效。-Altera Max 5 the GX series of schematic and pcb files, note that the capture and pdf format of the schematic and PCB files of the allegro format,
DAC.cmp
- 可编程逻辑器件CPLD/FPGA 该实验系统采用了独特的设计技术,使得实验用的可编程CPLD/FPGA 器件的I/O 接口与系统的相关器件采用固定连接-The programmable logic device CPLD/FPGA The experimental system uses a unique design technology, making the experiment with the programmable CPLD/FPGA device I/O interface wi
EDAshuzipinlvji
- 1)能够测量正弦波、三角波、锯齿波、矩形波等周期性信号的频率; 2)能直接用十进制数字显示测得的频率; 3)频率测量范围:1HZ~10KHZ切量程能自动切换; 4)输入信号幅度范围为0.5~5V,要求一起自动适应; 5)测量时间:T〈=1.5S;6)用CPLD/FPGA可编程逻辑器件实现 -1) capable of measuring the frequency of the sine wave, triangle wave, sawtooth wave, rectangular wave p
ct9999
- 很经典的数字钟程序CPLD / FPGA ,对初学者很有用。-Classic digital clock program CPLD/FPGA, useful for beginners.
Bspii_masttera
- 一种基于CPLD/FPGA的的SPI控制的IP核的实现spi -Based on CPLD/FPGA IP core SPI control realize spi
intro_to_quartus2_chinese
- 这个是介绍CPLD/FPGA的开发环境quartus2的文章,对初学者及开发人员应该会有一定的帮助。-This is to introduce the CPLD/FPGA development environment quartus2 in the article, there should be some help for beginners and developers.