搜索资源列表
PWM
- 使用FPGA/CPLD 输出固定占空比PWM波形。-using FPGA/CPLD output PWM waveform
shift-register
- FPGA/CPLD 的verilog移位寄存器代码。-verilog shift register code.
openocd-0.8.0
- OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support including: - (X)SVF playback to faciliate automated boundary scan and FPGA/CPLD programming - debug target support (
receive_spi
- verilog语言SPI通信,可用于CPLD以及FPGA-Verilog language SPI communications, can be used for CPLD and FPGA
freqency_meter
- 等精度原理数字频率计。cpld或fpga文件,和单片机.c文件。-digital frequency meter
RS485
- FPGA/CPLD实现RS485通信协议,在Quartus ii平台上进行Verilog编程仿真-FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
Sequence-Detector
- 序列检测器,开写为两个always语句,即为两段式有限状态机。将组合部分中的判断状态转移条件和产生输入再分开写,则为三段式有限状态机。 二段式在组合逻辑特别复杂时适用,但要注意需在后面加一个触发器以消除组合逻辑对输出产生的毛刺 。三段式描述方法虽然代码结构复杂了一些,但是换来的优势是:使FSM做到了同步寄存器输出,消除了组合逻辑输出的不稳定与毛刺的隐患,而且更利于时序路径分组,一般来说在FPGA/CPLD等可编程逻辑器件上的综合与布局布线效果更佳。-Sequence Detector
pinlvji
- 频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C-Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digita
ex5_mux
- 乘法器是众多数字系统中的基本模块。 从原理上说它属于组合逻辑范畴;但从工程实际设计上来说,它往往会利用时序逻辑设计的方法来实现,属于时序逻辑的范畴。通过这个实验使大家能够掌握利用 FPGA/CPLD 设计乘法器的思想,并且能够将我们设计的乘法器应用到实际工程中。 -The multiplier is the number of a digital system in the basic module. From the principle that it belongs to the combi
FPGA_fir
- FPGA/CPLD设计数字滤波器(FIR和IIR),已经仿真测试-FPGA/CPLD design digital filters (FIR and IIR), has simulation test
SCH
- DTMB GB20600-2006 terrestrial dig FPGA or CPLD reads the SD card IP tell us how to divide frequency f UMC 90nm design models. please re UMMC 90nm models. Please read the Bluetooth serial port via the pho scope FPGA code AG 0.35u
CAN-IP-Core
- CAN IP Core can硬件的IP核,用于cpld和fpga编程can接口-CAN IP Core
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程,可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元,外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008),可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
CPLDFPGA
- CPLD的详细教程,可以作为FPGA和CPLD的入门学习使用书-Lt /RTI &
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
基于Quartus-II-的FPGACPLD开发
- 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)