code ad98 use vhdl for director DDS

这是用DDS原理实现的频率计，能够测量1到999999HZ的待测信号，包括VHDL源程序以及成型的BDF文件。-This is achieved with a frequency meter DDS principle, can measure a signal under test to 999999HZ, including VHDL source code, as well as forming the BDF file.

Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation