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myfifo
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_bb
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_syn
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave0
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave1
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
FIFOinterface
- fifo(8):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
Flash_ROM_lab
- 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC ser
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
Operation
- Java程序模拟操作系统中先进先出、短作业优先、响应比高者优先的作业调度-Java FIFO simulation operating system, the short operating priority, in response to high priority of the job scheduling
cfifo_ptrs_binary
- system verilog fifo env
FX2_pipe_high_speed_io
- FX2Pipe is a small high speed USB transfer program which can pipe stdin into the FX2 FIFO or back from the FIFO to stdout.
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
Optimal
- 存储管理中页面置换算法性能测试 要求：设系统采用固定分配局部置换的存储分配策略，编写仿真程序对下述页面 置换算法进行性能测试，并对结果进行分析和比较。 (1) 最佳适应(Optimal)页面置换算法； (2) 先进先出(FIFO)页面置换算法； (3) 最近最久未使用(LRU)页面置换算法； (4) 最少使用(LFU)页面置换算法。 要求可适用于键盘输入和自动产生随机页面走向序列两种数据输入方式。-Memory management page repla
int_uart8051
- UART realization for at89c5131 with FIFO and interrupts.
asycnFIFO
- This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the computer networking industry to receive data at a particular frequency and transmit them at another frequency. An asynchronous FIFO has two diffe
FIFO.OPT
- 操作系统课程设计（源码和报告） 请求页式管理缺页中断模拟设计--FIFO、OPT-Operating systems curriculum design (source code and reports) request page management page fault analog design- FIFO, OPT
FIFO3
- 这个是8*4位的,FIFO,,大家可作参考资料-This is 8* 4-bit, FIFO,, We can make reference
FIFO
- FIFO，vhdl实现，希望可以有帮助,大家加油-FIFO VHDL
fifo123456
- 16*16位的先进先出队列FIFO程序,可作参考-16* 16-bit FIFO queue FIFO procedures, can be used for reference
FIFO
- 这个是对先进先出队列FIFO的理解,希望能帮到大家,-This is the understanding of FIFO FIFO queue and hope to help you