搜索资源列表
labQ2
- Source codes for verilog fifo for spartan 3
fifo
- A First in first out buffer in Verilog
fifo8
- FIFO 源程序，verilog HDL实现，自己验证过，没问题-FIFO source, verilog HDL to achieve their own verified, no problem
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
FIFO_test
- FIFO程序库,添加即可使用,一个非常实用的程序-FIFO library, add to the use of
cc2430_lib_and_app_1.0
- CC2430RF代码,DMA方式发送，FIFO方式-RF CC2430
CummingsSNUG2002SJ_FIFO2
- Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Virtualmemory
- 虚拟内存中四种置换算法: OPT/LRU/FIFO/时钟算法-Four types of virtual memory replacement algorithm: OPT/LRU/FIFO/clock algorithm
fifo
- To write data to the FIFO, present the data to be written and assert the write enable. At the next rising edge of the clock, the data will be written. For every rising edge of the clock that the write enable is asserted, a piece of data is written in
fifo_vhdl
- FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
fifodd
- 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
os
- 实现分页式存储地址转换过程，在此基础上实现请求分页的地址转换。实现请求页式地址转换中出现的缺页现象时，用到的先进先出FIFO、最近最久未使用LRU、最佳OPT置换算法。 -The realization of paging memory address translation process, in this based on the address translation request page. The realization of Page Address Translation req
2
- 在MCS-51系列单片机应用系统中利用FIFO芯片AL422B实现数字图像的静态存储-In the MCS-51 series single-chip applications using FIFO chip AL422B static digital image storage
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the
simulator
- ssd5 fifo.h 模拟打印机全部源代码-Printer simulation ssd5 fifo.h
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
use_SRAM_design_FIFO.pdf
- 利用sram技术设计的一个FIFO-failed to translate
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
FIFO
- 针对操作系统试验编程，实现fifo操作，可手动输入-Pilot program for the operating system to achieve fifo operation, can be manually input