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File
- 设计一个请求页式存储管理方案，并编写模拟程序实现之。页面淘汰算法采用 ① FIFO页面淘汰算法 ② LRU页面淘汰算法。-sorry
FIFOandLRU(java)
- 这是一个用java实现的模拟操作系统的进程调度的FIFO算法和LRU算法。程序默认设置的系统分配给进程的页面数为3个、-This is a simulation using java operating system to achieve the process of the FIFO scheduling algorithm and LRU algorithm. Procedures for the allocation of the default settings of the syste
fifo
- 先来先服务程序调度实现缺页中断调度算法驻留集大小，页面数，缺页中断数-fifo
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
FIFOSRC
- DSP uart窗口通信中的一种通信格式，FIFO模式的一个小程序-dsp serial communication uart communication first in first out-FIFO mode
FIFO
- 这是一个java做的显示数据的列表程序。-This is a java program to do list.
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
USB-based
- 基于USB接口Slave FIFO模式的核谱数据采集研究 -Slave FIFO Interface USB-based model study of nuclear spectroscopy data acquisition
aFifo
- 異步FIFO試作,寫入與讀取資料的時脈不同,藉此程式來達成-Test for asynchronous FIFO, write and read information on a different clock to the program to achieve
fpgafifo
- 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
fifo
- 页面置换算法，利用程序语言实现的 FIFO算法-fifo OS
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
VHDL
- 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
FIFO_Buffer
- Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects