搜索资源列表
FIFORAM
- FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
usb2.0
- usb2.0的传输的固件程序，驱动和主机程序的源码，usb芯片为cy7c68013 fifo模式-usb2.0 slove
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
fifo
- 这是一个串口通信的队列,单片机和电脑之间，单片机和单片机之间只要简单的调用函数就可以了。-This is a serial communication queue, single-chip computer and between computers, between single-chip MCU and a simple function call it.
SCI_TXRXFIFO_over
- SCI串口通信程序，使用FIFO功能，定时收发-SCI serial communication, the use of FIFO function, periodically send and receive
FIFO
- 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
fifo_test.v.tar
- code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
Asynchronous_FIFO_v6_1
- 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
fifo_syn
- 同步fifo并有详细的文档说明，希望对大家有帮助-Synchronous fifo and detailed documentation, we want to help
fifo-opt
- 四种页面置换算法，lru，二次机会，fifo，opt -lru,nur,fifo,opt
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapte
fifo_design
- 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
fifo.tar
- linux device driver for fifo algorithm
async_fifo
- 异步fifo 源程序代码 欢迎大家学习 用VHDL语言编写-asy fifo
Altera_FIFO
- Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
maxii_sch
- 采用EPM570作为核心，外接FIFO，RAM。可进行数据采集，采用60M时钟的ADC ADS830E。ADC前端电路需要改为差分输入方式以减小电路噪声。该电路经过实际检验可以使用，需要将JTAG电阻改为220以下或者短接。-EPM570 used as a core, external FIFO, RAM. Can be a data collection, using 60M clock ADC ADS830E. ADC front-end circuit differential inpu
SN74V3690-6PEU
- 我画的TI公司FIFO-SN74V3690-6PEU的最小系统版电路图，dxp的，有原理图和pcb，库文件也包括进来了.很好用。-I am painting the TI' s FIFO-SN74V3690-6PEU minimum system version of the circuit, dxp, there are schematic and pcb, library files also include a. It just works.
fifo
- 一个自己写的fifo代码，思路非常清晰,大家可以下载学习-good fifo
Async_fifo_Vijay_A._Nebhrajani
- Asynchronous FIFO Architectures - Designing a FIFO is one of the most common problems an ASIC designer comes across. This series of articles (by a popular author)is aimed at looking at how FIFOs may be designed -- a task that is not as simple as