搜索资源列表
fifo_verilog
- 用verilog 实现 fifo，宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs
IPcore_fifo_testbench
- 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
UART_FIFO
- Verilog 语言描述，基于FIFO设计的UART。Quartus 10中编译通过-Verilog language descr iption, based on the design of the UART FIFO
asy_fifo
- 用verilog实现异步fifo，通过仿真-Asynchronous with verilog fifo, the simulation
foio
- verilog语言写的先进先出（FIFO）电路-verilog language written in FIFO (FIFO) circuit
SPI
- 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
uartfifo
- 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
my_FIFO
- FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
rx_fifo
- verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Fifo_lk
- 简单好用的Fifo 128x32 Verilog-Fifo 128x32 Verilog
fifo_verilog
- FIFO的verilog实现,内含PDF说明和已建好工程。-Implementation of FIFO using verilog
uart
- 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
uart_1203_4
- MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o
System_Demons
- 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实
FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
fifo_uart
- 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
Syn_FIFO
- 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
uartfifo
- verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
versatile_fifo_latest.tar
- Verilog HDL语言编写的通用FIFO，让你更加了解FIFO的原理-versatile fifo based on verilog hdl.