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async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
uartfifo
- 利用verilog开发的串口FIFO程序，比较基本，包含完整的工程-The verilog developed serial FIFO procedures, more basic, including the complete project
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
024-DAC902
- verilog控制dac902的程序，先从fifo读取数据-the verilog control the dac902 procedures start fifo read data
022-FIFO_PRO
- verilog写的控制quartus自带fifo ip核的程序-verilog to write the control quartus own fifo ip nuclear program
aFIFO
- 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
sram_fifo_uart
- 用verilog HDL编写的SRAM+FIFO+UART模块，欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module
fifo_ctrl
- fifoctr 寄存器控制 verilog代码-FIFO ctr
aasyn_fiffos
- verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
LL
- verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
fifo_uart
- uart的verilog代码,包含fifo，并且采用过采样以防止噪声的干扰-uart verilog code
generic_fifos_latest.tar
- fifo的verilog代码，包含rtl，sim，testbench内容的verilog代码，完全可用-rtl code of a fifo
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
FIFO_V1
- 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
fifo_rd64
- 实现64位数据位宽的fifo的功能,用的是verilog代码。-Fifo functionality
uart_fifo_design
- verilog语言时序的异步读写FIFO，请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1