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exercise3
- 用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯,包括68013的固件以及fpga的代码(verilog)。摸了好久才调试通过的,特共享出来解救苍生!-fx2lp 68013 xilinx XC3s400 slave fifo
uart_fifo
- 带fifo的串口通信verilog设计,该设计为学习uart所用,完成PC端发送至fpga后fpga原数据返回,支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
spi_cbb
- 基于FPGA设计,verilog语言变成的,SPI通用接口模块,顶层已封装成类似标准的FIFO接口;提供仿真文件;仿真器为modelsim10.0c,波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
asyn_fifo2
- 采用Verilog语言,使用FPGA内部IP核FIFO模块,实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
class_fifo
- FPGA内部fifo的调用,使用Verilog对其进行编程-The FPGA internal fifo calls, use Verilog programming on it
uartfifo
- 串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。-uart communication
oscillo_1
- 简单数字示波器的verilog设计,涉及到时钟同步,FIFO的配置和使用,非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)