搜索资源列表
filter
- 基于VHDL的FIR数字滤波器的设计，可以自己修改参数设置滤波器阶数-FIR digital filter design based on VHDL, can modify the parameters to set the filter order
vhdl1
- 该程序实现了运用VHDL实现数字音频滤波，同时在FIR 滤波过程中减少了加法器和乘法器使用数量，大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
filter_lpm_shaping
- 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
FIR_poroje
- this project is about FIR FIlter By VHdl codes in the ISE.
fir_lms-adaptive-filter
- 采用VHDL语言编写的fir级联结构的LMS自适应滤波器，方便学习研究自适应滤波器有关参数实际实现的影响-Using VHDL language fir cascade structure of LMS adaptive filter, adaptive filter to facilitate study and research the impact of the actual implementation of the relevant parameters
fir_test01
- 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
myfir
- VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
xapp1161
- 多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数-Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
fir_noRom
- 有VHDL实现对复杂信号的16位fir滤波器-desgin the 16 bits FIR Filter by VHDL
filter
- 此程序是一个用VHDL语言编写的fir滤波器。经过了仿真验证，很好用。-This procedure is a VHDL language fir filter. After the simulation, very good use.
ddc1
- 数字上变频，包括DDC,CIC,补偿FIR,FIR。-Digital down conversion VHDL procedures, FIR, CIC filter
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
FIR_Filter1
- This a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.-This is a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.
filter_VHDL
- FIR filter design using VHDL for 32 bit signed coefficientand 32 bit input and decimation is 4 and its working good
FirFullSerial
- VHDL实现横向FIR滤波器，采用全串行结构，并附有matlab代码-VHDL implementation of the horizontal FIR filter, the use of a full serial structure, and with matlab code
FirHalfSerial
- VHDL采用半串行结构实现横向FIR滤波器，并附有matlab代码-VHDL uses a semi serial structure to achieve the horizontal FIR filter, and with matlab code
code1
- 9 tap fir fiter vhdl code
9tapfilt
- VHDL CODE FOR 9 TAP FIR FILTER
firfilt
- VHDL CODING FOR BASIC FIR FILTER
FIR_filter_based_on_fpga_in_VHDL
- 主要介绍基于FPGA的FIR滤波器的实现及其设计文档，VHDL语言-It introduces the realization and design documents FPGA-based FIR filters, VHDL language