搜索资源列表
The-Phase-Locked-Demodulation-
- 利用Altera公司推出的FPGA开发工具DSP Builder，对锁相解调算法中的主要部件：数控振荡器(NCO)、计算反正切的CORDIC模块和FIR低通滤波器进行了单独设计和仿真，最终完成了锁相解调系统的整体设计。-Designed and simulated major components of phase-locking Demodulation Algorithm independently, including: Number Controlled Oscillator(NCO)、
firtesmul
- 基于FPGA的FIR滤波器实现，并行乘法实现，运行速率快但占用资源多。-FPGA-based FIR filter, parallel multiplication achieve faster run rate but take up more resources.
graduate
- 基于fpga的IIR和FIR滤波器实现，里面有DA和AD模块，已经下载到板子上验证。-IIR and FIR filter fpga-based implementation, which has DA and AD modules have been downloaded to authenticate to the board.
1.High-Speed-FPGA-Implementation-of-FIR-Filter-fo
- related to VHDL language project
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR32
- 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
MultHalfBand
- 多级半带滤波器的FPGA实现,采用6级滤波器实现的采样频率由3200Hz降为50Hz的抽取系统，前5级为半带滤波器,最后一级为普通FIR滤波器-Multi-level half-band filter FPGA, using six filters for sampling frequencies 50Hz down to 3200Hz extraction system for the front five and a half-band filter, the last stage of
FPGA4JIIR
- 常用的数字滤波器有FIR数字滤波器和IIR数字滤波器｡ FIR数字滤波器具有精确的线性相位特性,在信号处理方面应用极为广泛,而且可以采用事先设计调试好的FIR数字滤波器IPCore来完成设计,例如Altera公司提供的针对Altera系列可编程器件的MegaCore,但是需要向Altera公司购买或申请试用版｡ 另外,对于相同的设计指标,FIR滤波器所要求的阶数比IIR滤波器高5~10倍,成本较高,而且信号的延迟也较大｡ IIR滤波器所要求的阶数不仅比FIR滤
scr
- 高级篇03：基于matlab和fpga的FIR滤波器设计-Senior chapter 03: matlab and fpga based FIR filter design
book3e
- 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
FIR_OVER
- 基于FPGA的FIR滤波器的设计，包括每个模块的设计和顶层原理图。-FIR filter design based on FPGA, including the design and top-level schematic of each module.
FIR_GEN
- 书籍《数字信号处理的FPGA实现》中关于有限长单位冲激响应滤波器FIR的源代码。-Book Digital Signal Processing FPGA Implementation on the finite impulse response filter FIR units of source code.
ditong50
- 基于fpga的fir滤波器，截止频率50k，阶数为32，用FDatool实现-Fpga based fir filter cutoff frequency 50k, order of 32, with FDatool achieve
FPGA32JFIR
- 基于FPGA的FIR滤波，希望对其它人有用-FPGA-based FIR filter, hope useful for other people! ! ! !
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
fpga_lms_filter_youhua
- 该文章介绍基于FPGA的FIR自适应滤波器的优化-The article introduces the optimization of FIR adaptive filter based on FPGA
fir_lms
- 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA
qam16-TX
- 基于Altera MAX10 FPGA的QAM16发送端设计代码，其中采用了MAX10 Fir滤波器IP核。供相关设计人员参考，或者进一步咨询本人。-Based on Altera MAX10 FPGA design of QAM16 the sender code, which uses the MAX10 Fir filter IP core. Related reference for designers, or further consultation himself.
FIR_lowpass
- 一种实用的基于FPGA的8阶高斯低通FIR滤波器-A practical 8 order gaussian low-pass FIR filter based on FPGA
FPGA_fir
- FPGA/CPLD设计数字滤波器（FIR和IIR），已经仿真测试-FPGA/CPLD design digital filters (FIR and IIR), has simulation test