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ad_converter
- 该代码可实现FPGA对AD转换器的控制，使用的是状态机-THE CODE CAN REALIZE THAT XILINX FPGA CONTROL AD CONVERTER BY USING STATEMENT MECHIN3
ads7835
- 基于ADS7835的高速AD采集芯片FPGA源码-ADS7835-based high-speed AD acquisition chip FPGA source code
TLC5510
- 采用超高速AD存储示波器程序设计。器件是采用TLC5510。用FPGA来控制实现。-The ultra high speed AD storage oscilloscope programming. Device is used TLC5510. Using FPGA to control the implementation.
parall_ad_da
- 并行DA和AD转换，能够成功实现其功能。已在FPGA开发板上验证。实现较高的数据转换精度。-Parallel DA and AD conversion, to successfully achieve its function. FPGA development board has been verified. Achieve higher precision data conversion.
ADC_TLC549_FPGA
- 用FPGA控制AD转换芯片tlc549实现AD转换-FPGA control AD conversion
AD_TLC549_TEST
- 本程序模块实现在FPGA内部的AD转换模块。模拟AD_TLC549转换器。-The program module within the AD converter in the FPGA module. Analog AD_TLC549 converter.
fpgacis
- 主要是通过使用FPGA利用CIS（接触式图像传感器）进行图像采集，通过AD转换之后把数据存储到FPGA里面开辟的FIFO-Mainly through the use of FPGA utilization of CIS (non-contact image sensor) image acquisition, through the data storage after AD transform to open the FIFO FPGA inside
1324135132324
- FPGA嵌入式编程，利用状态机实现AD转换功能，内附程序-FPGA embedded programming, using the state machine to achieve AD conversion function, enclosing the process
adc_tlc549_1
- tlc549 赛灵思fpga 串行AD输出八位分辨率-tlc549 fpga
ADCODE
- 用FPGA控制双ADC0809读写，用于双AD热备控制，用verilog实现-FPGA control with dual ADC0809 read and write, hot standby control for double AD, with verilog implementation
DFCPU
- 用FPGA做的一个32路AD程序(用VERLlog写的)-FPGA to do with a 32 AD program (written by VERLlog)
ADS2807ctrl
- ADS2807控制 FPGA板上采用TI的ADS2807高速AD芯片实现模拟信号的采集，最高速度可达50MPS,必须用FPGA进行控制。其工作时序图如下： -ADS2807 control FPGA board using TI' s ADS2807 high-speed AD chip analog signal acquisition, the maximum speed of up to 50MPS, must be controlled by FPGA. Timing di
RED--PCI-5.0
- 使用PCI9054作为接口芯片，通过FPGA实现PCI9054，SDRAM和AD之间的连接，本程序是以此为目的编写的.-PCI9054 interface chip used as a through FPGA implementation PCI9054, SDRAM, and the connection between AD, the program is prepared for this purpose.
ADSample_FPGA
- 开发环境为QuartusII。这是AD采样的verilog代码部分，在FPGA上硬件实现AD采样的一部分功能-Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
yinpinfangda
- 采用基于FPGA的频域加窗与反傅立叶变换的数字幅频均衡功 率放大器:此方案采用高速FPGA，以及配套的高速AD、DA 对信号进行采样，傅 立叶变换，在频域上对信号进行加窗操作，然后通过傅立叶反变换将波形还原。 以得到需要的频谱幅度。-FPGA-based frequency domain using the windowed Fourier transform with the number of pieces of anti-band equalizer amplifier: Th
DAC2ADC
- 利用FPGA，运用比较器和DA器件实现AD转换功能。高效，实用。-The use of FPGA, the use of comparator AD and DA conversion devices to achieve. Efficient and practical.
AD_store
- 利用FPGA，实现高速AD存储示波器功能。高效，实用。-Using FPGA, high-speed AD storage oscilloscope function. Efficient and practical.
AD_TEST
- 1、 本工程主要是把输人AD芯片的电压显示在数码管上。 2、 测试时，从JTAG口把AD_TEST.sof下载到FPGA，右边的4个数码管将会显示电压数据（单位：毫伏）。 -1, this project is mainly to AD input voltage displayed on the digital chip tube. 2 test, from the JTAG port to AD_TEST.sof download to the FPGA, the right o
connect_vhd
- 本程序的功能为检测输入信号范围是否在限定范围内，经ad转换器输入，经fpga芯片的Virtex4芯片输出来判断结果。-The functionality of the program for the detection of input signal range is within the limits, the ad converter input, the output fpga chip Virtex4 chip to determine the results.
adc_cvt
- FPGA控制AD采样一个周期采样32点，求给改成64点-FPGA controls the sampling period 32 AD sampling a point, seeking to change the 64-point