搜索资源列表
UART
- 基于FPGA的串并转换程序，8位并行。调试仿真成功，内附仿真波形文件-FPGA-based string and conversion program, 8-bit parallel. Debugging the simulation succeeds, the file containing the simulation waveforms
uart1
- vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port.
UART-VerilogHDL
- 基于verilog语言的uart的实现以及fpga的实现，及供参考-Based on the realization of the verilog language uart and the realization of the fpga, and for reference
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
RFID_UART
- 实现了rfid与fpga串口的数据通讯，fpga自发送-Achieve rfid serial data communication with the fpga, fpga from sending
demo7-uart
- FPGA EP2C5的串口代码，FPGA新手学习的很基础的代码-about the FPGA IC:EP2C5 uart code.it is use for the fresh one.
uart
- uart代码在FPGA开发板与电脑之间上实现其功能-uart code between the FPGA development board and computer
demo7-uart
- quartus 串口程序 可以通过开发板的串口对FPGA进行读写操作-the quartus serial program can development board through the serial port on the FPGA to read and write operations
UART-and-FPGA
- 基于FPGA的UART通信控制器 设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA Design and Implementation of hold. Used modelsim6.1f environment simulation.
UART
- FPGA实时监测RS232_RX信号是否有数据，若接收到数据，则把接收到的数据通过RS232_TX发送回对方。上位机使用的软件是串口调试助手（多模式课程网站下载）。在代码设计中，数据的波特率是可选的，可以根据需要进行配置，如9600bps，19200bps，38400bps，57600bps或115200bps。发送的数据帧格式为：1位起始位（保持一个传输位周期的低电平），8位数据，无校验位，1位停止位。-The FPGA real monitoring RS232_RX signal whet
fpga-mcu
- 利用uart接口，51单片机和FPGA完成16位宽的数据通信，包括数据的幷串转换等。-Uart interface 51 of microcontroller and FPGA 16-bit wide data communications, and including Bing string of data conversion.
UART
- fpga开发板与电脑进行串口通讯，实现了基于FPGA的串口接收发功能-fpga development board with a PC serial communications, FPGA-based serial port to receive hair
uart-of-fpga
- FPGA实现UART通信程序，verilog hdl语言实现的，好用-UART of FPGA
UART
- 基于FPGA的（Universal Asynchronous Receiver Transmitter，UART）串行通信设计论文-FPGA BASIC FOR （Universal Asynchronous Receiver Transmitter，UART）
FPGA---buld-gennerate
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
verilog--uart
- verilog实现uart功能的FPGA应用，适用于Cyclone 2系列-verilog uart function of FPGA applications in the Cyclone Series
fpga-uart
- 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
UART
- FPGA串口通信程序，Verilog HDL语言下的UART串口通信程序-Verilog HDL UART
uart
- uart的vhdl源码，实现fpga的通用串行异步收发接口的设计-the uart the vhdl source to achieve fpga universal serial asynchronous transceiver interface design
uart
- 用FPGA实现串口的收发功能，采用16背波特率的时钟对RXD采样，波特率的误差允许范围为4.8 -16 back baud rate clock on RXD serial transceiver functions FPGA implementation sampling, the range of allowable error of the baud rate of 4.8