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bysj7
- CVSD语音压缩的算法和程序流程.量阶δ能够自动地随输入信号平均斜率的大小而连续变化,译码输出信号实现了对输入信号的理想逼近,最后在可编程逻辑器件(FPGA)中实现了CVSD调制功能。-CVSD voice compression algorithm and the program flow. Volume bands can automatically input signal with an average slope of the size of continuous change, d
generic_fifos
- Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
EMIF_COM.rar
- 实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口,the interface for TI DSP and Xilinx s FPGAs
xapp460.zip
- 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）,Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
FPGAs
- 这是一篇英文文章，是用FPGA去实现信号处理-This is an English article, is to use FPGA to realize signal processing
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
fpgafft
- :文章针对目前数字信号处理中大量采用的快速傅立叶变换[FFT] 算法采用软件编程来处理的应用现状,在对FFT 算法进行 分析的基础上,给出了用FPGA[Field Programmable Gate Array] 实现的8 点32 位FFT 处理器方案,并得到了系统的仿真结果。 最后在Altera 公司FLEX10K系列FPGA 芯片上成功地实现了综合。-Based on the analysis of the FFT algorithm , a reasonable logic str
Digital Filter implementation by FPGA
- 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on
SAR-GMTI Range Compression Implementation in FPGAs
- SAR-GMTI_Range_Compression_Implementation_in_FPGAs 在多FPGA阵列上实现SAR距离脉压，超长点数脉压的FPGA实现-SAR-GMTI_Range_Compression_Implementation_in_FPGAs in the realization of multi-FPGA array SAR from the pulse pressure, long pulse pressure points to achieve th
fpga_security
- The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. This contribution attempts to provide a state-of-the-art descr ipt
analog_filter_VHDL
- Analog filter in Vhdl for fpgas
2_MotorControl
- this the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other-this is the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other
MotorControl
- this the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other-this is the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other
genode-fx-2009-03
- Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs.
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
Newnes.Design.Recipes.for.FPGAs.Jun.2007
- design recipe for fpga
Frequency_Divider_VhdlCode
- a very good frequency divider code for fpgas>
Serial_Input_Parallel_Output_ShiftRegister_VhdlCo
- a very good piso shift register for fpgas/>
ASK-OOK-FSK-BPSK
- MATLAB实现ASK, OOK, FSK, BPSK, QPSK, 8PSK调制源代码-Free Source Code for ASK, OOK, FSK, BPSK, QPSK, 8PSK Digital Modulation in FPGAs Xilinx using system generator (ASK, BPSK, FSK, OOK, QPSK)