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clkdiv
- 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
fdivision
- 基于verilog的分频器,以及相应的test bench-A frequency divider based on verilog
Binarydivider
- 采用verilog编写的二进制分频器,常用于频率变化场合-Binary frequency divider using verilog prepared, commonly used in the frequency occasions
fenpin
- 分频器的实现将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放-FDCT Frequency Divider
8fen
- 8分频器的VHDL源码，绝对正确，并且可根据本代码推导出各个2的幂数的分频器的编写原理。-FDCT Frequency Divider by VHDL .
ca60
- 60分频器，将主频分频，产生系统所需信号。-60 divider, the frequency divider to generate the necessary signal system.
COUNT
- 设计一个最大分频为225的分频器，将50MHz时钟作为输入。分频器可以通过计数器来实现，通过一个25位的计数器，然后在最后一位输出，则产生了一个最大分频为225的分频器。-Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out,
jiaocuofenpin
- 用硬件语言写了一个由8/9分频构成的无限不循环小数分频器，分频系数k=260/31-Written language with the hardware a 8/9 frequency divider consisting of an infinite non-recurring decimal, frequency factor k = 260/31
freqdiv_simple
- frequency divider using VHDL quite simple expecially for beginners cheers
fd
- 分频器（奇，偶，数分频）通过或的方法实现奇数分频，-frequency divider
fenpin
- 分频模块，实验板上的时钟频率太快，可以用分频模块来减小频率-Frequency modules, test board clock frequency too fast, the module can be used to reduce the frequency divider
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
BCD_COUNTER
- Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
div_freq
- VHDL program of frequency divider of 50hz at 3Hz 50 -> 3Hz for exemple
di
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
61EDA_D807
- VHDL数频分频器设计 整数，奇数，偶数，半数等的分频 -VHDL design of an integer number of frequency divider, odd, even, half of the frequency, etc.
fenpin
- 7分频器 是指将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放。在高质量声音重放时，需要进行电子分频处理-seven frequency divider
fenpin-FPGA
- 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from