搜索资源列表
frequency-divider
- 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
fenpin
- 通过FPGA设计实现的分频模块，仿真可以通过，适合初学者学习。-Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
fenpin
- 对m序列进行2ASK调制 包含分频器 m序列发生器 正弦信号发生器 二路选择器4个模块-process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
Frequency_divider
- 奇数分频器，通用分频器，占空比1:1分频器， 占空比非1:1分频器-Frequency divider
FENPIN48
- FPGA分频器，利用计数器计数，将外部晶振的48MHZ时钟分频为1MHZ-48M frequency division 1M frequency divider
clk_divR
- frequency divider into reglable frequence
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
diviseurFrquence50MhzTo1hz
- this file about frequency divider 50 MHz to 1 Hz used in 7-segment display
divider-achieved-by-verilog
- 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
4.5fenpingqi
- 基于FPGA的关于verilog语言的4.5分频器及其仿真波形图-FPGA based on verilog language frequency divider and its simulation waveform in figure 4.5
fenpinqi
- 数字分频器，包括分频器单位冲击响应及幅频响应-Digital frequency divider, including frequency divider unit impulse response and amplitude frequency response
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
half_integer
- 数控分频器：以2.5分频为例的半整数分频器-half-integer frequency divider
divider8
- 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware descr iption language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
fenpin5
- 五分频器的VHDL语言设计，改变相关参数，可得到其他分频器，便于学习VHDL语言-Five frequency divider VHDL language design, change the relevant parameters, you can get other dividers, easy to learn VHDL language
DDS
- 分频器，利用quartus软件或者modelsim软件对频率进行分频，也可在硬件上观察出对信号的分频-Frequency divider, quartus software or modelsim software is used to analyse the frequency divider, can also be used on hardware to detect the signal frequency division
Example5
- 数控分频器设计 数控分频器的功能就是当输入端给定不同的输入数据时， 分频器对输入时钟 信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器来设计 完成的，方法是将计数溢出位与预置数装载信号相接得到-NC NC divider divider design feature is that when the given input different input data, the frequency divider with a different frequency di
Freq_gen
- XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)